JPS6026934A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPS6026934A JPS6026934A JP13616383A JP13616383A JPS6026934A JP S6026934 A JPS6026934 A JP S6026934A JP 13616383 A JP13616383 A JP 13616383A JP 13616383 A JP13616383 A JP 13616383A JP S6026934 A JPS6026934 A JP S6026934A
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- JP
- Japan
- Prior art keywords
- electrode
- scanning
- stage
- selection
- potential
- Prior art date
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134336—Matrix
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Geometry (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal Display Device Control (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、複数のグループに分割されたマトリクスパタ
ーンが同一液晶セルに形成された、休止位相駆動多段液
晶マトリクスパネルに関するもので、その目的は相違す
る段間の接する部分のマトリクスパターンの工夫および
相違する段間の遷移時間での駆動波形の工夫により、表
示品質の高い液晶表示装置を提供することである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dormant phase drive multi-stage liquid crystal matrix panel in which matrix patterns divided into a plurality of groups are formed in the same liquid crystal cell, and the purpose is to control the contact areas between different stages. It is an object of the present invention to provide a liquid crystal display device with high display quality by devising a matrix pattern and devising drive waveforms at transition times between different stages.
休止位相駆動多段液晶マトリクスパネルの構成を第1図
に示す。説明を明確にするため2段の場合を示す。Mx
2Nのマトリクスとする。第1図は該パネルの平面図で
ある。1−1〜1−Mおよび2−1〜2−Mは信号電極
であり、一方の基板に形成されている透明導電体である
。FIG. 1 shows the configuration of a pause phase drive multi-stage liquid crystal matrix panel. For clarity of explanation, a two-stage case is shown. Mx
Let it be a 2N matrix. FIG. 1 is a plan view of the panel. 1-1 to 1-M and 2-1 to 2-M are signal electrodes, which are transparent conductors formed on one substrate.
6−1〜3−Nおよび4−1〜4−Nは走査電極であり
、他方の基板に形成されている透明導電体である。信号
電極1−1〜1−Mと走査電極3−1〜3−Nが1組の
マトリクスグループを形成する。6-1 to 3-N and 4-1 to 4-N are scanning electrodes, which are transparent conductors formed on the other substrate. Signal electrodes 1-1 to 1-M and scanning electrodes 3-1 to 3-N form one matrix group.
また信号電極2−1〜2−Mと走査電極4−1〜4−N
がもう1組のマトリクスグループを形成する。In addition, signal electrodes 2-1 to 2-M and scanning electrodes 4-1 to 4-N
form another matrix group.
この2段マトリクスパネルは、N分割の駆動波形を用い
て、すなわちN分割相当の液晶パネルの表示品質を保証
しながら2N本の走査電極を有する高分解能特性を呈す
。This two-stage matrix panel uses an N-divided driving waveform, that is, exhibits high-resolution characteristics with 2N scanning electrodes while guaranteeing display quality of a liquid crystal panel equivalent to N-divided liquid crystal panel.
休止位相駆動2段マトリクスパネルの駆動方法を以下に
示す。該駆動方法は電圧平均化法を変形したものである
。電圧平均化法の1駆動波形は4種の電位で構成される
。A method of driving the rest phase drive two-stage matrix panel is shown below. This driving method is a modification of the voltage averaging method. One drive waveform of the voltage averaging method is composed of four types of potentials.
すなわち走査電極選択電位、走査電極非選択電位、信号
電極選択電位および信号電極非選択電位である。休止位
相駆動は、これら4種の電位の他にさらに休止電位を有
する。休止位相駆動での各電極電位の時間変化を第1表
に示す。That is, they are a scanning electrode selection potential, a scanning electrode non-selection potential, a signal electrode selection potential, and a signal electrode non-selection potential. In addition to these four types of potentials, the resting phase drive also has a resting potential. Table 1 shows the temporal change in each electrode potential during rest phase driving.
第1表で時刻は1本の走査電極選択時間を単位としてい
る。すなわちNTSC方式のTV表示の場合には、水平
走査時間63.5μsecの整数倍の値を単位とする。In Table 1, time is expressed in units of time for selecting one scanning electrode. That is, in the case of NTSC TV display, the unit is a value that is an integral multiple of the horizontal scanning time of 63.5 μsec.
たとえば走査線数が全体で120本(N=60)の時は
、単位時間63.5x2=127μsec、240本(
N=120)の場合は63.5 μsec テある。For example, when the total number of scanning lines is 120 (N = 60), the unit time is 63.5 x 2 = 127 μsec, 240 lines (
In the case of N=120), it is 63.5 μsec.
第1表
時刻1〜Nは上段選択期間、時刻(N+]、)〜2Nは
下段選択期間である。垂直帰線期間とは第2N番目の走
査電極が選択終了してから第1番目の走査電極の選択が
開始するまでの期間である。In the first table, times 1 to N are upper selection periods, and times (N+], ) to 2N are lower selection periods. The vertical retrace period is a period from the end of selection of the 2Nth scan electrode to the start of selection of the first scan electrode.
第1表中の記号■は走査電極選択電位、Bは走査電極非
選択電位、Cは信号型、極選択電位、Dは信号電極非選
択電位、Eは休止電位である。走査電極6.4に印加さ
れる電位は走査電極選択電位■、走査電極非選択電位B
、および休止電位Eである。In Table 1, the symbol ■ is a scanning electrode selection potential, B is a scanning electrode non-selection potential, C is a signal type, electrode selection potential, D is a signal electrode non-selection potential, and E is a resting potential. The potentials applied to the scan electrodes 6.4 are scan electrode selection potential ■ and scan electrode non-selection potential B.
, and the resting potential E.
一方信号電極1.2に印加される電位は信号電極選択電
位C1信号電極非選択電位D、および休止電位Eである
。On the other hand, the potentials applied to the signal electrode 1.2 are the signal electrode selection potential C1, the signal electrode non-selection potential D, and the resting potential E.
つぎに各電位の印加タイミングを述べる。まず走査電極
6−1に走査電極選択電位■を印加する。Next, the application timing of each potential will be described. First, a scan electrode selection potential ■ is applied to the scan electrode 6-1.
他の上段電極3−2〜3−Nには走査電極非選択電位B
を印加する。The scanning electrode non-selection potential B is applied to the other upper electrodes 3-2 to 3-N.
Apply.
信号電極1−1〜1−Mには、表示パターンに依存して
信号電極選択電位Cまたは信号電極非選択電位りを印加
する。走査電極3−1との交点が表示の選択点である信
号電極には信号電極選択電位Cを、交点が表示の非選択
点である信号電極には、信号電極非選択電位りを印加す
る。A signal electrode selection potential C or a signal electrode non-selection potential is applied to the signal electrodes 1-1 to 1-M depending on the display pattern. A signal electrode selection potential C is applied to the signal electrode whose intersection with the scanning electrode 3-1 is a selection point for display, and a signal electrode non-selection potential R is applied to the signal electrode whose intersection is a non-selection point for display.
階調表示を行なう場合には、走査電極3−1選折中に、
信号電極への印加電圧を表示階調に依存して信号電極選
択電位Cと非選択電位りのデー−ティ比を制御、すなわ
ちパルス幅変調を行なう。When performing gradation display, during scanning electrode 3-1 selection,
The voltage applied to the signal electrode is controlled depending on the display gradation to control the duty ratio between the signal electrode selection potential C and the non-selection potential, that is, pulse width modulation is performed.
走査電極3−1選択終了後、走査電極3−2゜6−3、
・・・・・・3−Nと、つぎつぎに選択状態とする。上
段走査電極乙のいずれかが選択されている上段選択期間
は、下段走査電極4および下段信号電極2には、休止電
位Eを印加する。すると下段走査電極4および下段信号
電極2で構成される下段マ)1722部の液晶層は、零
ボルトが印加されたことになり、クロストークが発生し
ない。After scanning electrode 3-1 is selected, scanning electrode 3-2゜6-3,
. . . 3-N, the selection state is made one after another. During the upper selection period when any of the upper scanning electrodes B is selected, the resting potential E is applied to the lower scanning electrode 4 and the lower signal electrode 2. Then, zero volts are applied to the liquid crystal layer in the lower part 1722 formed by the lower scanning electrode 4 and the lower signal electrode 2, and no crosstalk occurs.
上段マトリクス部の最下端の走査電極3−N選択終了後
、下段マトリクス部の最上端の走査電極4−1に走査電
極選択信号■を印加して選択状態とする。After the selection of the scanning electrode 3-N at the lowermost end of the upper matrix section is completed, the scanning electrode selection signal (2) is applied to the scanning electrode 4-1 at the uppermost end of the lower matrix section to bring it into a selected state.
下段マトリクス部の信号電極には、上述の上部マl−1
722部の信号電極について述べたと同様に。The signal electrode of the lower matrix section has the above-mentioned upper matrix l-1.
Same as described for the signal electrode of part 722.
走査電極の選択と同期して、信号電極選択電位Cまたは
信号電極非選択電位りを表示パターンに依存して印加す
る。In synchronization with the selection of the scanning electrodes, a signal electrode selection potential C or a signal electrode non-selection potential C is applied depending on the display pattern.
また上段マトリクス部の走査電極6と信号電極1はとも
に、下段マドIJクス部選折中は、休止電位Eを印加す
る。Further, the resting potential E is applied to both the scanning electrode 6 and the signal electrode 1 in the upper matrix section during the selection of the lower matrix IJ section.
すなわち下段マ) IJクス選択中は折中段マトリクス
部の液晶層への印加電圧は零ボルトでありクロストーク
を生じない。That is, while the IJ box is selected in the lower row matrix section, the voltage applied to the liquid crystal layer in the middle row matrix section is zero volts, and no crosstalk occurs.
下段マ) 1722部の走査電極4−Nの選択が終了後
、該マトリクスパネルの全電極すなわち1.2.6およ
び4は上段マトリクス部の走査電極6−1が選択時刻に
なるまですべて休止電位Eが印加され、液晶層電圧は零
となる。After the selection of scanning electrode 4-N in the lower matrix section 1722 is completed, all electrodes of the matrix panel, ie, 1, 2, 6 and 4, are at rest potential until the scanning electrode 6-1 in the upper matrix section reaches the selection time. E is applied, and the liquid crystal layer voltage becomes zero.
以上述べた休止位相駆動多段液晶マ) IJクスパネル
では、液晶層に印加される電圧が零となる休止位相期間
が、クロストーク低減の作用をするため、表示品質の低
下を伴なうことなく高分解能化を得ている。In the above-mentioned rest phase drive multi-stage liquid crystal display (IJ) panel, the rest phase period during which the voltage applied to the liquid crystal layer is zero acts to reduce crosstalk, so high performance can be achieved without deteriorating display quality. Resolution has been achieved.
すなわち走査電極3(4)と信号電極1(2)で構成さ
れる上(下)段マトリクス部の液晶層は、上(下)段選
択期間は電圧平均化法のN分割相当の駆動波形が印加さ
れるが、上(下)段選択期間以外は零ボルトであるので
クロストークに寄与しない。よってN分割相当の表示品
質を保証しつつ、上、下段合計して2N本の分解能を有
する液晶マトリクスパネルを得る。In other words, the liquid crystal layer in the upper (lower) matrix section, which is composed of the scanning electrode 3 (4) and the signal electrode 1 (2), has a drive waveform equivalent to N divisions in the voltage averaging method during the upper (lower) stage selection period. However, since it is 0 volts except during the upper (lower) stage selection period, it does not contribute to crosstalk. Therefore, a liquid crystal matrix panel having a total resolution of 2N lines in the upper and lower stages is obtained while guaranteeing display quality equivalent to N divisions.
休止位相駆動多段液晶マトリクスパネルはマトリクスパ
ターンが段に分割されているので段間の表示に関して以
下の欠点がある。Since the matrix pattern of the pause phase drive multi-stage liquid crystal matrix panel is divided into stages, there are the following drawbacks regarding the display between the stages.
第1の欠点は股間の分離水平線が見えることである。第
1図のFで示した段間を拡大した第2図(a)を用いて
説明する。3−(N−1)、3−Nは上段マトリクス部
の走査電極、4−1.4−2は下段マ) 1722部の
走査電極である。The first drawback is that the horizontal separation line between the crotches is visible. This will be explained using FIG. 2(a), which is an enlarged view of the gap indicated by F in FIG. 1. 3-(N-1) and 3-N are scan electrodes in the upper matrix section, and 4-1, 4-2 are scan electrodes in the lower matrix section.
5.6.7は走査電極間の約20μm幅の間隙である。5.6.7 is a gap of approximately 20 μm width between scanning electrodes.
6は段間の間隙であり膜中の間隙である5、7と区別さ
れる。膜中の間隙5(7)は信号電極1(2)のパター
ン化された透明導電体を有するが、間隙6はいかなる電
極をも有しない。6 is a gap between stages, which is distinguished from 5 and 7, which are gaps in the membrane. Gap 5 (7) in the membrane has a patterned transparent conductor of signal electrode 1 (2), while gap 6 does not have any electrode.
透明導電体の透過率は、80%程度であるので。The transmittance of a transparent conductor is about 80%.
透明導電体のある膜中の間隙と透明電極のない段間の間
隙は相違して見える。すなわち段間の間隙6が上段、下
段を分離する白い水平線として視認され表示品質が低下
する。Gaps in the film with transparent conductors and gaps between stages without transparent electrodes look different. That is, the gap 6 between the stages is visually perceived as a white horizontal line separating the upper stage and the lower stage, and the display quality deteriorates.
つぎの欠点は、段の隣接部で画素パターンが非対称にな
ることである。第2図(b)の拡大図を用いて説明する
。10.12は上段マトリクス部の信号電極、11.1
6は下段マトリクス部の信号電極である。The next drawback is that the pixel pattern becomes asymmetrical in adjacent parts of the tiers. This will be explained using the enlarged view of FIG. 2(b). 10.12 is the signal electrode of the upper matrix section, 11.1
6 is a signal electrode in the lower matrix section.
第2図(b)(イ)は走査電極が形成された基板と信号
電極が形成されたもう一方の基板の重ね合わせずれ幅が
零の場合、第2図(b)(ロ)はずれ幅がIl+の場合
である。重ね合わせずれ幅が零の場合は、上段マトリク
ス部の画素14.下段マトリクス部の画素15の画素幅
はともに1gであり、走査電極幅と一致する。また14
.15の画素間距離はl。であり上、下マトリクス部の
間隙幅と一致する。Figure 2 (b) (a) shows that when the overlapping width of the substrate on which the scanning electrode is formed and the other substrate on which the signal electrode is formed is zero, and Figure 2 (b) (b) shows that the misalignment width is zero. This is the case for Il+. If the overlay deviation width is zero, pixel 14 in the upper matrix section. The pixel widths of the pixels 15 in the lower matrix portion are both 1 g, which matches the width of the scanning electrodes. Also 14
.. The distance between pixels of 15 is l. This corresponds to the gap width between the upper and lower matrix parts.
一方1重ね合わせずれ量11の場合には、上段マトリク
ス部の最下段画素16と下段マトリクス部の最上段画素
17の間隙幅は、lo+Lと、他の部分の間隙幅l。よ
り増加するので、その存在が上、下マトリクス部を分離
する水平線として強く視認され、表示品質が著しく低下
する。重ね合わせずれ量11の値は走査電極間間隙l。On the other hand, in the case of one overlay deviation amount of 11, the gap width between the bottom pixel 16 of the upper matrix section and the top pixel 17 of the lower matrix section is lo+L, and the gap width of the other parts is l. As the number of lines increases, its presence is strongly visible as a horizontal line separating the upper and lower matrix portions, resulting in a significant deterioration in display quality. The value of the overlay deviation amount 11 is the gap l between scanning electrodes.
010%以下であることが望ましい。It is desirable that it be 0.010% or less.
I!oとして一般的な値20μmを用いると、11は2
μm以下である。工業的生産規模にて、重ね合わせ精度
2μm以下を得ることは非常に困難であり、パネル歩留
まり値を極めて低いものとしていた。I! Using a common value of 20 μm for o, 11 becomes 2
It is less than μm. It is extremely difficult to obtain an overlay accuracy of 2 μm or less on an industrial production scale, resulting in an extremely low panel yield value.
本発明は休止位相駆動多段マ) IJクスパネルの上記
欠点を除去した安価で表示品質の高いパネルを提供すべ
くなされたもので、以下に詳細を述べる。The present invention has been made to provide an inexpensive panel with high display quality that eliminates the above-mentioned drawbacks of the pause phase drive multi-stage IJ panel, and will be described in detail below.
説明を明確にするため、2段マトリクスパネルを中心に
述べる。本発明の実施例による電極パターンの平面図を
第3図に示す。第1図と同機能を有す構成要素は同記号
を用いる。ドツト数は第1図と同様にMx2N個である
。第3図は、従来例の第1図の走査電極3−N、4−1
を接続し、かつ両走査電極の間隙も電極とした、段間走
査電極18を設けたことを特徴とする。For clarity of explanation, we will focus on the two-stage matrix panel. A plan view of an electrode pattern according to an embodiment of the present invention is shown in FIG. The same symbols are used for components having the same functions as those in FIG. The number of dots is Mx2N as in FIG. FIG. 3 shows scanning electrodes 3-N and 4-1 of FIG. 1 in the conventional example.
The feature is that an inter-stage scanning electrode 18 is provided, which connects the two scanning electrodes and also serves as an electrode in the gap between both scanning electrodes.
第3図の部分Gを拡大して第4図に示す。段間走査電極
18が従来の欠点をすべて除(。第1の欠点である役向
の走査電極間隙19.21の透過率と段間の間隙20の
透過率の相違は以下の理由で均一化できる。段間の間隙
20は段間走査電極18の透明導電体が存在するので、
信号電極1.2の透明導電体が配設されている役向の間
隙19.21と透過率がほぼ等しくなり、第1の欠点が
除去される。Part G of FIG. 3 is enlarged and shown in FIG. The interstage scanning electrode 18 eliminates all the conventional drawbacks (the first drawback, the difference between the transmittance of the scanning electrode gap 19 and 21 and the transmittance of the interstage gap 20, is made uniform for the following reason. Since the transparent conductor of the interstage scanning electrode 18 exists in the gap 20 between the stages,
The transmittance is approximately equal to that of the active gap 19.21 in which the transparent conductor of the signal electrode 1.2 is disposed, and the first drawback is eliminated.
つぎに、重ね合わせずれに付随して生じる第2の欠点に
ついて述べる。本発明のパターンでは、上段マドIJク
ス部の最下端画素22の下辺と下段マトリクス部の最上
端画素26の上辺の距離は、信号電極1の下辺と信号電
極2の上辺間の距離のみで決まり、重ね合わせずれ量に
依存せず一定である。よって第2の欠点も除去された。Next, a second drawback that occurs due to misalignment will be described. In the pattern of the present invention, the distance between the lower edge of the lowermost pixel 22 in the upper matrix section and the upper edge of the uppermost pixel 26 in the lower matrix section is determined only by the distance between the lower edge of the signal electrode 1 and the upper edge of the signal electrode 2. , is constant regardless of the amount of overlay deviation. The second drawback was thus also eliminated.
しかし、股間走査電極18の導入は、あらたな不都合を
生じる。これは、第1表に示した駆動波形に従って液晶
層駆動を行なうと、上段マトリクス部の最下端画素群と
下段マ) IJクス部の最上段画素群は、それらの走査
電極として段間走査電極18を共有しているので、第1
表の時刻NとN+1に連続して走査電極選択電位が印加
され、他の画素に比較して実効値が増加するので、他の
画素と画素間るさが著しく相違する欠点が発生すること
である。However, the introduction of the crotch scanning electrode 18 brings about new inconveniences. When the liquid crystal layer is driven according to the drive waveform shown in Table 1, the lowest pixel group in the upper matrix section and the uppermost pixel group in the IJ section will be connected to the inter-stage scanning electrodes as their scanning electrodes. 18, so the first
The scanning electrode selection potential is applied continuously at times N and N+1 in the table, and the effective value increases compared to other pixels, resulting in a drawback that the inter-pixel harshness is significantly different from other pixels. be.
本発明は、上記不都合を以下のような駆動波形を考案す
ることにより解決した。第2表に本発明の各電極電位の
時間変化を示す。垂直帰線期間にはすべての電極に休止
電位Eを印加する。The present invention has solved the above-mentioned disadvantages by devising the following drive waveform. Table 2 shows the temporal change in each electrode potential of the present invention. During the vertical retrace period, resting potential E is applied to all electrodes.
まず上段マトリクス部の走査電極6−1〜3−(N−1
)について説明する。上段選択期間のそれぞれの選択時
刻に走査電極選択電位■を印加し、上段選択期間のそれ
ぞれの選択時刻以外は走査電極非選択電位Bを印加する
。First, the scanning electrodes 6-1 to 3-(N-1
) will be explained. A scanning electrode selection potential ■ is applied at each selection time in the upper selection period, and a scanning electrode non-selection potential B is applied at times other than each selection time in the upper selection period.
また下段選択期間の時刻N−1−1には、すべてに走査
電極選択電位■を印加する。その後の下段選択期間は走
査電極非選択電位Bを印加する。つぎに走査電極18に
ついて説明する。Furthermore, at time N-1-1 of the lower selection period, the scanning electrode selection potential ■ is applied to all the electrodes. During the subsequent lower selection period, the scan electrode non-selection potential B is applied. Next, the scanning electrode 18 will be explained.
第2表
時刻NとN+1に走査電極選択電位■を印加する。それ
以外の土(下)段選択期間は走査電極非選択電位Bを印
加する。Scanning electrode selection potential ■ is applied at times N and N+1 in Table 2. During the other soil (lower) stage selection periods, the scanning electrode non-selection potential B is applied.
つぎに下段マトリクス部の走査電極4−2〜4〜Nにつ
いて説明する。上段選択期間中の時刻1〜N−1は走査
電極非選択電位Bをすべて印加する。時刻Nには走査電
極選択電位■をすべてに印加する。Next, the scanning electrodes 4-2 to 4-N in the lower matrix section will be explained. At times 1 to N-1 during the upper stage selection period, the scan electrode non-selection potential B is applied to all the scan electrodes. At time N, the scanning electrode selection potential ■ is applied to all.
下段選択期間は、各走査電極の選択時刻にそれぞれの走
査電極に走査電極選択電位■を、他の時刻には走査電極
非選択電位Bをそれぞれの走査電極に印加する。In the lower selection period, the scan electrode selection potential ■ is applied to each scan electrode at the selection time of each scan electrode, and the scan electrode non-selection potential B is applied to each scan electrode at other times.
つぎに上段マトリクス部の信号電極1−1〜1−Mへの
印加電位について説明する。上段選択期間は走査選択電
位に同期して、表示情報に依存して信号電極選択電位C
または信号電極非選択電位りを印加する。下段選択期間
中の、時刻N+1に走査電極選択電位■を印加し、他の
期間は走査電極非選択電位Bを印加する。Next, the potentials applied to the signal electrodes 1-1 to 1-M in the upper matrix section will be explained. During the upper selection period, the signal electrode selection potential C is synchronized with the scanning selection potential and depends on the display information.
Alternatively, a non-selection potential is applied to the signal electrode. During the lower stage selection period, the scanning electrode selection potential ■ is applied at time N+1, and the scanning electrode non-selection potential B is applied during the other periods.
つぎに下段マトリクス部の信号電極2−1〜2−Mへの
印加電位について説明する。上段選択期間中の時刻1〜
N−1は走査電極非選択電位Bを印加し、時刻Nは走査
電極選択電位のを印加する。下段選択期間中は、走査電
極選択電位■に同期して、表示情報に依存して信号電極
選択電位Cまたは信号電極非選択電位りを印加する。Next, the potentials applied to the signal electrodes 2-1 to 2-M in the lower matrix section will be explained. From time 1 during the upper selection period
At time N-1, the scan electrode non-selection potential B is applied, and at time N, the scan electrode selection potential is applied. During the lower stage selection period, a signal electrode selection potential C or a signal electrode non-selection potential R is applied depending on the display information in synchronization with the scanning electrode selection potential ■.
最後に、以上のように各電位を走査電極と信号電極に印
加した場合の、液晶層への印加電圧を第2表の下端の液
晶電圧の項に示す。第2表でHは(走査電極選択電位■
−信号電極選択電位C)または(走査電極選択電位■−
信号電極非選択電位D)を示す。また■は(走査電極選
択電位B −信号電極選択電位C)または(走査電、極
非選択電位B−信号電極非選択軍位D)である。Finally, the voltages applied to the liquid crystal layer when each potential is applied to the scanning electrode and the signal electrode as described above are shown in the liquid crystal voltage section at the bottom of Table 2. In Table 2, H is (scanning electrode selection potential■
-Signal electrode selection potential C) or (scanning electrode selection potential■-
The signal electrode non-selection potential D) is shown. Also, ■ is (scanning electrode selection potential B - signal electrode selection potential C) or (scanning electrode, pole non-selection potential B - signal electrode non-selection position D).
上段マ) IJクス部の代表面素として走査電極6−1
と信号電極1−1の交点画素を取り上げる。Upper row ma) Scanning electrode 6-1 as a representative surface element of the IJ box part
Let us take up the intersection pixel between the signal electrode 1-1 and the signal electrode 1-1.
当画素の液晶層の両端電圧は時刻1はH1時刻2〜Nは
I、下段選択期間および垂直帰線期間は零ボルトである
。下段マトリクス部の代表面素として走査電極4−2と
信号電極2−1の交点画素を取り上げる。この画素の液
晶層の両端電圧は、垂直帰線期間および上段選択期間は
零ボルト、下段選択期間の時刻N+1および時刻N+3
〜2NはI1時刻N+2はHである。The voltage across the liquid crystal layer of the pixel is H1 at time 1, I at time 2 to N, and zero volts during the lower selection period and the vertical retrace period. The intersection pixel between the scanning electrode 4-2 and the signal electrode 2-1 is taken up as a representative surface element in the lower matrix section. The voltage across the liquid crystal layer of this pixel is zero volts during the vertical retrace period and the upper selection period, and at time N+1 and time N+3 during the lower selection period.
~2N is I1 time N+2 is H.
すなわち上(下)段マトリクス部の画素は上(下)段選
択期間のみ電圧が印加され、下(上)段選択期間および
垂直帰線期間は零ボルトである。That is, a voltage is applied to the pixels in the upper (lower) matrix section only during the upper (lower) row selection period, and zero volts are applied during the lower (upper) row selection period and the vertical retrace period.
第2表の特徴は、上(下)段マトリクス部が選択期間に
ある特上(下)段マl−IJクス部の走査電極と上(下
)段マ) IJクス部の信号電極には電圧平均化法に従
って電位を印加し、また上(下)段マトリクス部が非選
択期間中は、上(下)段マトリクス部の走査電極と信号
電極には、段間走査電極選択時は走査電極選択信号を、
段間走査電極非選択時は走査電極非選択信号を印加する
ことである。The characteristics of Table 2 are that the upper (lower) matrix section is in the selection period, and the scanning electrodes of the upper (lower) IJ section and the signal electrodes of the upper (lower) IJ section are A potential is applied according to the voltage averaging method, and during the period when the upper (lower) matrix section is not selected, the scan electrodes and signal electrodes of the upper (lower) matrix section are connected to the scanning electrodes when the interstage scanning electrode is selected. select signal,
When the interstage scanning electrode is not selected, a scanning electrode non-selection signal is applied.
上(下)段選択時以外の期間は上(下)段マトリクス部
の液晶層への印加電圧を零ボルトに保つことにより、電
圧平均化法N分割駆動相当の表示品質を保証して、1駆
動分割数の2倍の2N本の走査線を有する高分解能マト
リクスパネルを得る。By keeping the voltage applied to the liquid crystal layer of the upper (lower) matrix section at zero volts during periods other than when the upper (lower) stage is selected, display quality equivalent to voltage averaging method N-division driving is guaranteed. A high-resolution matrix panel having 2N scanning lines, which is twice the number of driving divisions, is obtained.
つぎに段数かに段の多段マ) IJクスパネルの駆動方
法を述べる。第1段から順に第に段まで走査するとする
。垂直帰線期間は全段の走査電極と信号電極に休止電位
を印加する。Next, we will explain how to drive a multi-stage IJ panel. It is assumed that scanning is performed sequentially from the first stage to the second stage. During the vertical retrace period, a resting potential is applied to the scanning electrodes and signal electrodes of all stages.
第1段の走査電極と信号電極の印加電位を述べる。第1
段が選択期間の場合は、電圧平均化法に従って電位を印
加する。第1段が非選択期間中は、パネル中のいずれか
の股間走査電極の選択時は、第1段の走査電極と信号電
極の両電極にともに走査電極選択電位を、パネル中の段
間走査電極が非選択時は、走査電極非選択電位を印加す
る。The potentials applied to the first stage scanning electrodes and signal electrodes will be described. 1st
When a stage is in a selection period, a potential is applied according to the voltage averaging method. During the period when the first stage is not selected, when any of the crotch scan electrodes in the panel is selected, the scan electrode selection potential is applied to both the first stage scan electrode and the signal electrode, and the scan electrode selection potential is applied to the interstage scan electrode in the panel. When the electrode is not selected, a scan electrode non-selection potential is applied.
最後に走査電極選択電位■、走査電極非選択電位B、信
号電極選択電位C1信号電極非選択電位D、休止電位E
の波形を述べる。各波形を第5図に示す。Finally, scanning electrode selection potential ■, scanning electrode non-selection potential B, signal electrode selection potential C1, signal electrode non-selection potential D, resting potential E
Describe the waveform of Each waveform is shown in FIG.
第5図の横軸は時間であり、1本の走査線の選択時間で
ある。液晶印加電圧を交流化するため、選択時間の半分
の時間で電圧を折り返す。第5図のaは
J〒−1−4a/(a2−2a十N) −・”(11を
最大にする値である。(1]式でNは各段の走査電極数
である。第5図に示した電圧■。は液晶の閾値電圧をv
thとしたとき
を満足する値である。(2)式でLはある走査電極が選
択されてから再度選択されるまでの時間と1本の走査電
極が選択されている時間の比である。休止電位Eは任意
の波形でよいが、低消費電力を保証するため直流が望ま
しく、回路を簡単にするため第6図の鳩または零ボルト
がよい。The horizontal axis in FIG. 5 is time, which is the selection time of one scanning line. In order to change the voltage applied to the liquid crystal to alternating current, the voltage is turned back at half the selected time. In FIG. 5, a is the value that maximizes J〒-1-4a/(a2-2a×N)-・"(11. In equation (1), N is the number of scanning electrodes in each stage. The voltage shown in Figure 5 is the threshold voltage of the liquid crystal.
This is a value that satisfies when th. In equation (2), L is the ratio of the time from when a certain scan electrode is selected until it is selected again to the time during which one scan electrode is selected. The resting potential E may have any waveform, but direct current is preferable to ensure low power consumption, and to simplify the circuit, it is preferably pigeon or zero volt as shown in FIG.
なお1本発明は1本の信号電極を複数電極にして、等制
約に走査線数を増加する、いわゆる多重マトリクス方式
においても有効である。Note that the present invention is also effective in a so-called multiple matrix method in which one signal electrode is made into a plurality of electrodes and the number of scanning lines is increased with equal constraints.
以上述べたように1本発明は段間の見栄えが良好な高品
質表示で、製造歩留まりが高く安価な液晶表示装置を提
供するものである。As described above, one object of the present invention is to provide an inexpensive liquid crystal display device that has a high quality display with good appearance between stages, has a high manufacturing yield, and is inexpensive.
第1図は従来の実施例の平面図。
第2図は従来の実施例の重ね合わせずれを示す拡大平面
図。
第3図は本発明の実施例の平面図。
第4図は本発明の実施例の拡大平面図。
第5図は本発明の印加電圧波形図である。
1・・・・・・上段信号電極。
2・・・・・・下段信号電極、
6・・・・・・上段走査電極。
4・・・・・・下段走査電極、
18・・・・・・段間走査電極。
噂 (o k
第5図
■ B CDFIG. 1 is a plan view of a conventional embodiment. FIG. 2 is an enlarged plan view showing misalignment in the conventional embodiment. FIG. 3 is a plan view of an embodiment of the invention. FIG. 4 is an enlarged plan view of an embodiment of the present invention. FIG. 5 is an applied voltage waveform diagram of the present invention. 1... Upper stage signal electrode. 2... Lower stage signal electrode, 6... Upper stage scanning electrode. 4...Lower scanning electrode, 18...Inter-stage scanning electrode. Rumor (ok Figure 5 ■ B CD
Claims (2)
しへ基板と、該走査電極とほぼ直交した複数にグループ
化された信号電極を内面に形成した基板を、内面を対向
させて配置し、該2枚の基板間に液晶を配設し、複数の
グループ化された多段マトリクス部を形成し、多段マト
リクス部を順次選択期間とし、該段マトリクス部が選択
期間中に該段マ) IJクス部を構成する走査電極を順
次選択し、選択された走査電極には走査電極選択電位を
印加し、非選択の走査電極には走査電極非選択電位を印
加し、該選択期間中のマトリクス部の信号電極には1表
示情報に依存して信号電極選択電位または信号電極非選
択電位を印加し、該段マ) IJクス部が非選択期間に
は、該走査電極および該信号電極にはともに同電位を印
加する休止位相駆動多段液晶マトリクスパネルにおいて
、となり合う2段のマトリクス部の隣接する端部の走査
電極を接続し、接続された2本の走査電極間の間隙も電
極として1本化した段間走査電極を形成し、選択期間中
の該段マトリクス部内の選択された走査電極には走査電
極選択電位を印加し、非選択の走査電極には走査電極非
選択電位を印加し、該選択期間中のマ) IJクス部の
信号電極には、表示情報に依存して信号電極選択電位ま
たは信号電極非選択電位を印加し、該段マトリクス部が
非選択期間中は、該段マトリクス部の走査電極と信号電
極にはともに、パネル中のいずれかの段間走査電極の選
択時は、走査電極選択電位を印加し、パネル中の段間走
査電極が非選択時は、走査電極非選択電位を印加し、垂
直帰線期間中はパネル中の全走査電極および全信号電極
に休止電位を印加することを特徴とする液晶表示装置。(1) A substrate having a plurality of grouped scanning electrodes formed on its inner surface and a substrate having a plurality of grouped signal electrodes formed on its inner surface substantially perpendicular to the scanning electrodes are arranged with their inner surfaces facing each other. , a liquid crystal is disposed between the two substrates, a plurality of grouped multi-stage matrix parts are formed, the multi-stage matrix parts are sequentially set as a selection period, and the stage matrix part is set in the selection period during the selection period. The scanning electrodes constituting the matrix section are sequentially selected, a scanning electrode selection potential is applied to the selected scanning electrodes, a scanning electrode non-selection potential is applied to the unselected scanning electrodes, and the matrix section during the selection period is A signal electrode selection potential or a signal electrode non-selection potential is applied to the signal electrode depending on the display information, and when the IJ section is in the non-selection period, both the scanning electrode and the signal electrode are applied. In a pause phase drive multi-stage liquid crystal matrix panel that applies the same potential, scan electrodes at adjacent ends of two adjacent matrix sections are connected, and the gap between the two connected scan electrodes is also converted into a single electrode. A scan electrode selection potential is applied to the selected scan electrode in the row matrix portion during the selection period, a scan electrode non-selection potential is applied to the unselected scan electrode, and a scan electrode non-selection potential is applied to the unselected scan electrode. During the selection period, a signal electrode selection potential or a signal electrode non-selection potential is applied to the signal electrode of the IJ section depending on the display information, and during the non-selection period of the stage matrix section, the signal electrode of the IJ section is applied. When any inter-stage scanning electrode in the panel is selected, a scanning electrode selection potential is applied to both the scanning electrode and the signal electrode, and when no inter-stage scanning electrode in the panel is selected, the scanning electrode is not selected. A liquid crystal display device characterized in that a potential is applied and a resting potential is applied to all scanning electrodes and all signal electrodes in the panel during a vertical retrace period.
第1項記載の液晶表示装置。(2) The liquid crystal display device according to claim 1, wherein the number of stages is two.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13616383A JPS6026934A (en) | 1983-07-26 | 1983-07-26 | Liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13616383A JPS6026934A (en) | 1983-07-26 | 1983-07-26 | Liquid crystal display device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6026934A true JPS6026934A (en) | 1985-02-09 |
JPH0534654B2 JPH0534654B2 (en) | 1993-05-24 |
Family
ID=15168790
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13616383A Granted JPS6026934A (en) | 1983-07-26 | 1983-07-26 | Liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6026934A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61124990A (en) * | 1984-11-22 | 1986-06-12 | 沖電気工業株式会社 | Lcd matrix panel driving circuit |
JPS61173922U (en) * | 1985-04-16 | 1986-10-29 | ||
JPS6298329A (en) * | 1985-10-25 | 1987-05-07 | Casio Comput Co Ltd | Liquid crystal display element |
JPS62121426A (en) * | 1985-11-22 | 1987-06-02 | Hitachi Ltd | Liquid crystal display |
JP2010197576A (en) * | 2009-02-24 | 2010-09-09 | Sony Corp | Display device and method of manufacturing same |
JP2011138154A (en) * | 2011-02-18 | 2011-07-14 | Sony Corp | Display device and method of manufacturing the same |
-
1983
- 1983-07-26 JP JP13616383A patent/JPS6026934A/en active Granted
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61124990A (en) * | 1984-11-22 | 1986-06-12 | 沖電気工業株式会社 | Lcd matrix panel driving circuit |
JPH0549085B2 (en) * | 1984-11-22 | 1993-07-23 | Oki Electric Ind Co Ltd | |
JPS61173922U (en) * | 1985-04-16 | 1986-10-29 | ||
JPS6298329A (en) * | 1985-10-25 | 1987-05-07 | Casio Comput Co Ltd | Liquid crystal display element |
JPS62121426A (en) * | 1985-11-22 | 1987-06-02 | Hitachi Ltd | Liquid crystal display |
JP2010197576A (en) * | 2009-02-24 | 2010-09-09 | Sony Corp | Display device and method of manufacturing same |
JP2011138154A (en) * | 2011-02-18 | 2011-07-14 | Sony Corp | Display device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0534654B2 (en) | 1993-05-24 |
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