JPS60241276A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPS60241276A JPS60241276A JP59097772A JP9777284A JPS60241276A JP S60241276 A JPS60241276 A JP S60241276A JP 59097772 A JP59097772 A JP 59097772A JP 9777284 A JP9777284 A JP 9777284A JP S60241276 A JPS60241276 A JP S60241276A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- guard ring
- inp
- semiconductor layer
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001747 exhibiting effect Effects 0.000 claims description 2
- 230000012010 growth Effects 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 240000002329 Inga feuillei Species 0.000 abstract 1
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 40
- 230000015556 catabolic process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 2
- 241001122767 Theaceae Species 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H01L31/03042—
-
- H01L31/107—
Landscapes
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to semiconductor devices.
（従来技術とその問題点）
動作部を構成するｐｎ接合の周辺にガードリング部を有
する半導体素子においては、ガードリング部の降伏電圧
と動作部の降伏電圧との差を大きくすることが特性上、
信頼性上で重要である。この降伏電圧差を大きくするた
めに、たとえば安田らにより第４４回応用物理学会学術
講演会講演予稿１５６ページに「埋込み構造をもつＩ−
■族ＡＰＤの検討」と題して発表された講演においては
、第１図ｄに示した構造をしている。この構造は、以下
のようにして製作される。すなわちｎ＋−１ｎＰ基板１
上にｎ−１ｎＰバツフア一層２ 、 ｎ−−ＩｎＧａＡ
ｓ層３ 、 ｎ−−ＩｎＧａＡｓＰ層４．ｎ−ＩｎＰ層
５を連続成長させ（Ｚｉａ図）、その後ｎ−１ｎＰを選
択的に除去し凸部６を形成する（Ｊ、ｐｂ図）。その後
ｎ−−ＩｎＰ層７を成長させ（ａ１′、Ｐ ｃ図ン凸部
６を中心に位置合わせを行い、ガードリング部８とｐ＋
部９を形成した（Ｊ＋ｄ図）、この様な製造方法により
得られる素子はｐ＋部の空乏層のみｎ−ＩｎＰ層に拡が
り、ガードリング部の空乏層はｎ −１ｎＰ中に留める
ことができる。それによりガードリング部の降伏電圧を
下げることなく動作部の降伏゛亀圧のみ下げることが可
能となり、両者の降伏電圧差を大きくすることができる
。しかし、ｎ−ＩｎＰ１脅５上にｎ −ＩｎＰ層７ を
成長させるさいに熱劣化層が発生することや凸部６での
段差によりｎ−−ＩｎＰ層７には凸部６にそった転位が
発生することなどにより、素子のＩ−■特性が著しく劣
化する問題があった。(Prior art and its problems) In a semiconductor element having a guard ring part around a pn junction constituting an active part, it is characteristically necessary to increase the difference between the breakdown voltage of the guard ring part and the breakdown voltage of the active part. ,
Important for reliability. In order to increase this breakdown voltage difference, Yasuda et al., for example, wrote in the 44th Japan Society of Applied Physics Conference Proceedings Proceedings, page 156, ``I
In the lecture titled ``Study of Family APD'', the structure was as shown in Figure 1d. This structure is fabricated as follows. That is, n+-1nP substrate 1
n-1nP buffer layer 2 on top, n--InGaA
s layer 3, n--InGaAsP layer 4. The n-InP layer 5 is continuously grown (Zia diagram), and then the n-1nP layer is selectively removed to form the convex portion 6 (J, pb diagram). After that, the n--InP layer 7 is grown (a1', Pc), and the guard ring part 8 and p+
In the device obtained by such a manufacturing method in which the portion 9 is formed (Fig. J+d), only the depletion layer in the p+ portion extends to the n-InP layer, and the depletion layer in the guard ring portion can be kept in the n-1nP layer. This makes it possible to reduce only the breakdown voltage of the active part without lowering the breakdown voltage of the guard ring part, and it is possible to increase the difference in breakdown voltage between the two parts. However, when growing the n-InP layer 7 on the n-InP1 layer 5, a thermally degraded layer is generated and the dislocations along the protrusion 6 occur in the n-InP layer 7 due to the step at the protrusion 6. There has been a problem in that the I-■ characteristics of the device are significantly deteriorated due to such occurrence.
（発明の目的）
本発明は、このような従来の欠点を除去せしめてガード
リング部降伏電圧と動作部の降伏電圧との差を大きくす
ることが可能でかつＩ−■特性の劣化のない半ｉＨ素子
を提供することにある。(Object of the Invention) The present invention eliminates such conventional drawbacks, makes it possible to increase the difference between the breakdown voltage of the guard ring part and the breakdown voltage of the active part, and provides a half-half without deterioration of the I-■ characteristics. The purpose is to provide an iH element.
（本発明の構成）
本発明の素子は、第１導電型を示す第１の半導体層上に
第１の半導体層よりも不純物濃度の旨い第１導゛亀型の
第２の半導体層を備え、第２の半導体層中にｐｎ接合を
備え、該ｐｎ接合の外周にこのｐｎ接合の外縁部を内包
するようにして少なくとも第１の半導体層に達する深さ
のカードリング部を備え、さらに該ガードリング部の外
縁部を含む外周部が少なくとも第１の半導体層に達する
深さまでその表面が除去されている構成きなっている。(Structure of the Present Invention) The device of the present invention includes a second semiconductor layer of a first conductivity type, which has a higher impurity concentration than the first semiconductor layer, on a first semiconductor layer exhibiting a first conductivity type. , a pn junction is provided in the second semiconductor layer, a card ring portion is provided at the outer periphery of the pn junction and has a depth reaching at least the first semiconductor layer so as to include the outer edge of the pn junction; The outer circumferential portion including the outer edge of the guard ring portion has a structure in which the surface thereof is removed to a depth that reaches at least the first semiconductor layer.
（構成の詳細な説明）
本発明は、上述の構成をとることにより従来技術の問題
点を解決した。すなわち従来技術でＩ−■特性の劣化原
因である２回に分けた結晶成長及び凸部６への段差のあ
るウェーハに対する結晶成長を除去し、平坦なウェーハ
への１回の連続成長により製造可能とすることにより成
長時における熱劣化層の発生及び凸部による転位の発生
をなくし、Ｉ−Ｖ％性の劣化を防いだ６才だ、素子動作
部を高濃度層である第１の半導体中に形成し、ガードリ
ング部の外周部の高濃度層をとり除きガードリング部を
低濃度層のみとすることでガードリング部の降伏電圧と
動作部の降伏電圧の差を大きくしている。(Detailed Description of Configuration) The present invention solves the problems of the prior art by adopting the above-described configuration. In other words, by eliminating the two separate crystal growths and the crystal growth on wafers with steps to the convex portions 6, which are the causes of deterioration of the I-■ characteristics in the conventional technology, manufacturing is possible by one continuous growth on a flat wafer. This eliminates the generation of heat-degraded layers during growth and the generation of dislocations due to convex parts, and prevents the deterioration of I-V% characteristics. By removing the high concentration layer on the outer periphery of the guard ring portion and leaving the guard ring portion with only a low concentration layer, the difference between the breakdown voltage of the guard ring portion and the breakdown voltage of the active portion is increased.
（実施例）
以下本発明の実施例について図面を参照して詳細に説明
する。第２図は本発明の実施例を示す断面向で、ｎ −
ＩｎＰ基板１０上にｎ−ＩｎＰ バッファ層１１、ｎ−
−Ｉ ｎＧａＡｓ ｍ （不純物１度５ Ｘ Ｉｎ！５
ｃｖａ ’厚さ４ ｔｔｍ） １２． ｎ−−Ｉｎ（）
ａＡｓＰ層（不純物濃度５ Ｘ ＩＱ”Ｃｍ−３，厚さ
０５μｍ）１３．ｎ−−ＩｎＰ層（不純物、７５１ｉ
５ Ｘ １０” ｃｍ−３，厚さ１．５μｆｆ１）１４
． ｎ−Ｉｎｋ’層（不純・物濃度Ｉ Ｘ １０”傭−
１，厚さ３μｍ）１５を連続成長した（ｔｅａ図）。そ
の後Ｂｅ＋のイオン注入法によりガードリング部１６を
ｎ−ＩｎＰ層１層中４中ｒ＋７− ＩｎＧａＡｓＰ １
１１３とｎ−−ＩｎＰ層１層面４の界面から約０．５μ
ｍの位置）に形成した。その後Ｚｎの熱拡散法ｌこより
ｐ＋部エフをｎ −Ｉ ｎ Ｐ層１５ 中（深さ２μｍ
）に形成した（ｉｙｔ−ｂ図）。その後ガードリング部
１６の外周部のみをｎ−−ＩｎＰ層１層面４するまで除
去した（４！ｆｃ図）。(Example) Examples of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a cross-sectional view showing an embodiment of the present invention, with n −
An n-InP buffer layer 11, an n-
-InGaAs m (Impurity 1 degree 5 X In!5
cva' thickness 4 ttm) 12. n--In()
aAsP layer (impurity concentration 5 x IQ”Cm-3, thickness 05μm) 13.n--InP layer (impurity, 751i
5 X 10” cm-3, thickness 1.5μff1) 14
．． n-Ink' layer (Impurity concentration I x 10")
1, thickness 3 μm) was continuously grown (tea diagram). Thereafter, the guard ring portion 16 is formed by Be+ ion implantation to form r+7- InGaAsP 1 in 4 of the n-InP layers.
Approximately 0.5μ from the interface between 113 and n--InP layer 1 layer surface 4
m position). After that, the p+ part F was deposited in the n -I n P layer 15 (depth 2 μm) using Zn thermal diffusion method.
) (Figure iyt-b). Thereafter, only the outer peripheral part of the guard ring part 16 was removed until the n--InP layer 1 layer surface 4 was removed (Figure 4!fc).
（発明の効果）
本発明と従来方法による素子（前記文献及び第１１’Ａ
Ｋ示した製造方法ｌこよる）のＩ −Ｖ特性の比較を第
３図に示す、従来の素子のＩ −Ｖ特性１８は空乏層が
２回成長時に発生した熱劣化層に達する約１０Ｖ付近で
急激に増加する、また逆バイアス電圧をさらに印加する
と凸部埋込により発生した転位により暗電流が増加する
ことから降伏電圧の０．９倍の逆バイアス電圧印加時で
のＨＩＥ流は約ＩＸ］０’Ａであった。しかし１本発明
による素子の１−４特性１９は前記熱劣化及び転位を発
生しないために降伏電圧の０．９倍の逆バイアス電圧印
加時での暗電流は約２ Ｘ １Ｏ−８Ａと大幅な低減が
なされた。(Effect of the invention) Elements according to the present invention and the conventional method (the above document and No. 11'A
Figure 3 shows a comparison of the I-V characteristics of the manufacturing method shown in Figure 3.The I-V characteristics of the conventional element18 are around 10V, which reaches the thermally degraded layer generated when the depletion layer grows twice. Furthermore, when the reverse bias voltage is further applied, the dark current increases due to dislocations generated by the embedding of the convex part. Therefore, when a reverse bias voltage of 0.9 times the breakdown voltage is applied, the HIE current is approximately IX. ]0'A. However, 1-4 characteristic 19 of the device according to the present invention is that the above-mentioned thermal deterioration and dislocation do not occur, so the dark current when a reverse bias voltage of 0.9 times the breakdown voltage is applied is as large as about 2 × 1O-8A. A reduction was made.
以上詳細に述べた通り１本発明によれば熱劣化・転位等
の結晶欠陥を無くすことができ、そのため大幅なＪ −
Ｖ％性の改善をはかることができる。As described above in detail, 1. According to the present invention, crystal defects such as thermal deterioration and dislocation can be eliminated, and therefore a large amount of J −
It is possible to improve the V% property.
尚１本発明ではＡＰＤ （アバランシェ・フォト・ダイ
オード）を例に用いたが、ガードリングをゼする他の半
導体素子にも適用可能であり、また実施例として第１の
半導体層にｎ −ＩｎＰ７〜を第２の半導体層としてｎ
−ＩｎＰ層を用いたが半導体材料・導電型ｌごはよらず
有効であることは言うまでもない。In the present invention, an APD (avalanche photo diode) is used as an example, but it is also applicable to other semiconductor devices that have a guard ring. n as the second semiconductor layer
Although the -InP layer is used, it goes without saying that it is effective regardless of the semiconductor material and conductivity type.
第１図は従来の半導体素子の製造工程を示す図、第２図
は本発明を通用した半導体素子の製造工程を示す図、第
３悶は従来の素子と本発明による素子のＩ −Ｖ特性を
ぞれぞれ示す図である。
図において、
１ 、ｌｏ−ｎ＋−ＩｎＰ基板、２ 、］ｌ・・ｎ−Ｉ
ｎＰバッファ一層、３ 、１２・・ｎ−−１ｎＧａＡｓ
層、 ４ 、１３・・・ｎ −Ｉｎ（ＪａＡｓＰ層、５
、１５・−ｎ−ＩｎＰＩｖＩ−７、１４・・・ｎ −
Ｉｎ２層、 ６・・・凸部、８．１６・・・ガードリン
グ部、９．１７・・・ｐ十部、 １８・・・従来の素子
のＩ−Ｖ特性、１９・・・本発明による素子のＩ−Ｖ特
性をそれぞれ示す。
代理人弁理士 内照 晋
第 １ 図
差バイアス電圧 （Ｖ）FIG. 1 is a diagram showing the manufacturing process of a conventional semiconductor device, FIG. 2 is a diagram showing the manufacturing process of a semiconductor device using the present invention, and the third figure is a diagram showing the I-V characteristics of the conventional device and the device according to the present invention. FIG. In the figure, 1, lo-n+-InP substrate, 2, ]l...n-I
nP buffer single layer, 3, 12...n--1nGaAs
layer, 4, 13...n-In (JaAsP layer, 5
, 15·-n-InPIvI-7, 14...n −
In2 layer, 6... Convex part, 8.16... Guard ring part, 9.17... P ten part, 18... I-V characteristics of conventional element, 19... According to the present invention The IV characteristics of each element are shown. Representative Patent Attorney Susumu Uchiteru 1 Diagram difference bias voltage (V)
Claims (1)
体層よりも不純物濃度の高い第１導電徴の第２の半導体
層を備え、第２の半導体層中にｐｎ接合を備え、該ｐｎ
接合の外周にこのｐｎ接合の外縁部を内包するようにし
て少なくとも第１の半導体層に達する深さのガードリン
グ部を備え、さらに該ガードリング部の外縁を含む外周
部が少なくとも第１の半導体層に達する深さまでその表
面が除去されていることを特徴とする半導体素子。A second semiconductor layer having a first conductivity characteristic with a higher impurity concentration than the first semiconductor layer is provided on the first semiconductor layer exhibiting the first conductivity type, and a pn junction is provided in the second semiconductor layer. , the pn
The outer periphery of the junction includes a guard ring portion having a depth that reaches at least the first semiconductor layer so as to include the outer edge of the pn junction, and the outer periphery including the outer edge of the guard ring portion includes at least the first semiconductor layer. A semiconductor device characterized in that its surface is removed to a depth that reaches a layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59097772A JPS60241276A (en) | 1984-05-16 | 1984-05-16 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59097772A JPS60241276A (en) | 1984-05-16 | 1984-05-16 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60241276A true JPS60241276A (en) | 1985-11-30 |
Family
ID=14201136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59097772A Pending JPS60241276A (en) | 1984-05-16 | 1984-05-16 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60241276A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021034644A (en) * | 2019-08-28 | 2021-03-01 | 住友電気工業株式会社 | Light receiving element |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5212076A (en) * | 1975-07-18 | 1977-01-29 | Kazuo Terada | Method of backing and reinforcing structure |
-
1984
- 1984-05-16 JP JP59097772A patent/JPS60241276A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5212076A (en) * | 1975-07-18 | 1977-01-29 | Kazuo Terada | Method of backing and reinforcing structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021034644A (en) * | 2019-08-28 | 2021-03-01 | 住友電気工業株式会社 | Light receiving element |
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