JPS60218873A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60218873A JPS60218873A JP7416084A JP7416084A JPS60218873A JP S60218873 A JPS60218873 A JP S60218873A JP 7416084 A JP7416084 A JP 7416084A JP 7416084 A JP7416084 A JP 7416084A JP S60218873 A JPS60218873 A JP S60218873A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- conductive region
- silicon
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 5
- 238000003754 machining Methods 0.000 abstract description 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 230000001010 compromised effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に係り、たとえば、高
周波領域で使用するトランジスタに好適な自己整合技術
を利用した製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and for example, to a method of manufacturing a semiconductor device using self-alignment technology suitable for transistors used in a high frequency region.
特に、高周波領域で使用するトランジスタにおいて、そ
の使用周波数をより高くし、その周波数特性を改善する
には、高度な微細加工が必要であり、その加工精度を高
めるために、従来から自己整合技術が利用されている。In particular, for transistors used in the high frequency range, advanced microfabrication is required to increase the operating frequency and improve the frequency characteristics, and self-alignment technology has traditionally been used to improve the machining accuracy. It's being used.
周知のように、自己整合技術は、半導体装置の製造工程
上、複数のマスク間の整合精度は無視できるものであり
、マスク合わせで避けることができない誤差を考慮する
必要がないなどの点を特徴としている。As is well known, self-alignment technology is characterized by the fact that the alignment accuracy between multiple masks can be ignored in the semiconductor device manufacturing process, and there is no need to consider errors that cannot be avoided in mask alignment. It is said that
しかしながら、近時、高周波領域で使用される半導体装
置のディメンションの縮小化が高まり、パターンの微細
化によって従来の自己整合技術では、マスクずれによる
歩留りの低下が生じている。However, in recent years, the dimensions of semiconductor devices used in high-frequency regions have been increasingly reduced, and as patterns have become finer, conventional self-alignment techniques have suffered from a decrease in yield due to mask misalignment.
この発明は、その自己整合性をより高め、微細加工の精
度を向上させるとともに、歩留りの改善および半導体装
置の信頼性を高めることを目的とする。The object of the present invention is to further enhance the self-alignment, improve the precision of microfabrication, and improve the yield and reliability of the semiconductor device.
すなわち、この発明は、−導電形の半導体基板上に、そ
の表面層に形成した反対導電形の第１の導電領域を覆う
ように絶縁膜を形成する工程と、この絶縁膜上に窒化膜
を形成する工程と、この窒化膜に前記第１の導電領域上
の前記絶縁膜を露出させる２以上の開口部を形成する工
程と、これらの開口部の内の１または２以上のものから
前記絶縁膜を除き前記第１の導電領域を露出させる工程
と、この露出した第１の導電領域に反対導電形の第２の
導電領域を形成する工程と、この第２の導電領域を形成
した部分以外の開口部を介して前記絶縁膜を除き第１の
導電領域を露出させる電極形成用開口を形成する工程と
からなり、自己整合性を高め、微細加工の精度を改善し
たものである。That is, the present invention includes the steps of forming an insulating film on a semiconductor substrate of -conductivity type so as to cover a first conductive region of the opposite conductivity type formed on the surface layer thereof, and forming a nitride film on this insulating film. forming two or more openings in the nitride film to expose the insulating film on the first conductive region; and removing the insulating film from one or more of these openings. a step of exposing the first conductive region by removing the film; a step of forming a second conductive region of an opposite conductivity type on the exposed first conductive region; and a step other than the portion where the second conductive region is formed. forming an electrode forming opening that exposes the first conductive region by removing the insulating film through the opening, thereby increasing self-alignment and improving precision of microfabrication.
以下、この発明を図面に示した実施例を参照して詳細に
説明する。Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
第１図はこの発明の半導体装置の製造方法の実施例を示
し、（Ａ）ないしくＧ）はそれを製造工程順に示したも
のである。FIG. 1 shows an embodiment of the method for manufacturing a semiconductor device according to the present invention, and (A) to G) show the method in the order of manufacturing steps.
第１図において、（Ａ）は、−導電形の半導体基板とし
てのシリコン基板２に、反対導電形の第１の導電領域で
あるベース領域４を形成し、その表面に絶縁膜である酸
化シリコン（Ｓｉｎｇ）膜６を形成したものである。In FIG. 1, (A) shows that a base region 4, which is a first conductive region of an opposite conductivity type, is formed on a silicon substrate 2, which is a semiconductor substrate of a − conductivity type, and a silicon oxide film, which is an insulating film, is formed on the surface of the base region 4, which is a first conductive region of an opposite conductivity type. (Sing) film 6 is formed.
すなわち、ベース領域４は、酸化シリコン膜６に開口部
８を形成し、シリコン基板２を露出させて気相成長法に
より形成し、あるいは、開口部８に５００〜８００人の
酸化シリコン膜６を形成した後、イオン注入により形成
する。前者の方法でベース領域４が形成される場合には
、その表面を覆うように、５００〜８００人の酸化シリ
コン膜６を形成する。That is, the base region 4 is formed by forming an opening 8 in the silicon oxide film 6 and exposing the silicon substrate 2 by vapor phase growth, or by depositing 500 to 800 silicon oxide films 6 in the opening 8. After forming, it is formed by ion implantation. When the base region 4 is formed by the former method, a silicon oxide film 6 of 500 to 800 layers is formed to cover the surface thereof.
次に、（Ｂ）に示すように、酸化シリコン膜６の表面に
、それを覆う窒化膜として窒化シリコン（Ｓｉ３Ｎ４）
膜１０を気相成長法（ＣＶ Ｄ）によって形成する。Next, as shown in (B), silicon nitride (Si3N4) is deposited on the surface of the silicon oxide film 6 as a nitride film covering it.
Film 10 is formed by vapor phase epitaxy (CVD).
次に、（Ｃ）に示すように、この窒化シリコン膜１０に
は、２以上の開口部、この実施例では第１の開口部１２
Ａと、２つの第２の開口部１２Ｂを選択的に形成した後
、第１の開口部１２Ａを選択的に露出させ、その他の部
分を覆うレジストマスク１４を形成する。Next, as shown in (C), this silicon nitride film 10 has two or more openings, in this embodiment, a first opening 12.
After selectively forming the first opening 12A and the two second openings 12B, a resist mask 14 is formed to selectively expose the first opening 12A and cover the other portions.
第１の開口部１２Ａは、第２の導電領域であるエミッタ
およびその電極形成用開口、第２の開口部１２Ｂは、ベ
ース電極形成用開口にそれぞれ対応し、これらは、たと
えばレジストマスク１４を形成した後、酸化シリコン膜
６が損なわれないようなエツチング処理で形成するもの
とする。The first opening 12A corresponds to an opening for forming an emitter as a second conductive region and its electrode, and the second opening 12B corresponds to an opening for forming a base electrode, and these are used to form, for example, the resist mask 14. After that, the silicon oxide film 6 is formed by an etching process that does not damage it.
次に、（Ｄ）に示すように、窒化シリコン膜１０の開口
部１２Ａから露出している酸化シリコン膜６を、窒化シ
リコン膜１０をマスクとしたエツチング処理により除い
て、開口部１２Ａにベース領域４を露出させた後、全表
面を覆うように多結晶層として多結晶シリコン層１６を
形成する。この多結晶シリコン層１６には、ベース領域
４とは反対導電形の第２の導電領域を形成するための不
純物をドープし、またはイオン注入などによりベース領
域４とは反対導電形の第２の導電領域を形成するための
、たとえば、Ｎ形の不純物を注入してもよい。Next, as shown in (D), the silicon oxide film 6 exposed from the opening 12A of the silicon nitride film 10 is removed by an etching process using the silicon nitride film 10 as a mask, and a base region is formed in the opening 12A. After exposing 4, a polycrystalline silicon layer 16 is formed as a polycrystalline layer so as to cover the entire surface. This polycrystalline silicon layer 16 is doped with an impurity to form a second conductive region having a conductivity type opposite to that of the base region 4, or is doped with an impurity to form a second conductive region having a conductivity type opposite to that of the base region 4 by ion implantation. For example, N-type impurities may be implanted to form a conductive region.
次に、（Ｅ）に示すように、第１の開口部１２Ａを覆う
部分の多結晶シリコンＪｉｉ１６をエツチングによって
選択的に残すとともに、その全面を覆うように２，００
０〜３．０００人の酸化シリコン膜１８を気相成長法に
より形成し、これをベーキングにより熱拡散させて第１
の導電領域の内部に第２の導電領域としてのエミッタ領
域２０を形成する。Next, as shown in (E), the portion of the polycrystalline silicon Jii 16 that covers the first opening 12A is left selectively by etching, and a 2,000 ml film is etched to cover the entire surface.
A silicon oxide film 18 of 0 to 3,000 layers is formed by vapor phase epitaxy, and then thermally diffused by baking to form the first silicon oxide film 18.
An emitter region 20 as a second conductive region is formed inside the conductive region.
次に、（Ｆ）に示すように、酸化シリコンｌ＊１８の上
にレジストマスク２２を形成した後、このレジストマス
ク２２には、窒化シリコン膜１０の第１および第２の開
口部１２Ａ、１２Ｂに対応する位置にそれより大きい開
口部１４Ａ、１４Ｂを形成し、その開口部１４Ａ、１４
Ｂから酸化シリコン膜１８を除いて多結晶シリコン層１
６を露出させ、これをエミッタ電極形成用開口とすると
ともに、窒化シリコン１１！１０をマスクにして酸化シ
リコン膜６を除いて第２の開口部１２Ｂからベース領域
４を露出させ、これをベース電極形成用開口とする。Next, as shown in (F), after forming a resist mask 22 on the silicon oxide l*18, this resist mask 22 includes the first and second openings 12A and 12B of the silicon nitride film 10. Larger openings 14A, 14B are formed at positions corresponding to the openings 14A, 14B.
Polycrystalline silicon layer 1 excluding silicon oxide film 18 from B
6 is exposed and used as an opening for forming an emitter electrode, and the base region 4 is exposed from the second opening 12B by removing the silicon oxide film 6 using silicon nitride 11!10 as a mask and used as a base electrode. Use as a forming opening.
次に、（Ｇ）に示すように、レジストマスク２２を除い
た後、第１の開口部１２Ａを覆う多結晶シリコン層１６
には、エミッタ電極２４、第２の開口部１２Ｂには、ベ
ース電極２６を形成して高周波用トランジスタが得られ
る。なお、Ｅはそのエミフタ、Ｂはそのベースを示す。Next, as shown in (G), after removing the resist mask 22, a polycrystalline silicon layer 16 covering the first opening 12A is formed.
A high frequency transistor is obtained by forming an emitter electrode 24 and a base electrode 26 in the second opening 12B. Note that E indicates its emifter and B indicates its base.
この場合、多結晶シリコン層１６は、エミッタ電極２４
の一部を成している。In this case, the polycrystalline silicon layer 16 is connected to the emitter electrode 24.
It forms part of the
したがって、このような製造方法によれば、シリコン基
板２の表面に形成した酸化シリコン膜６・を覆う窒化シ
リコン膜１０に、選択的に開口部１２Ａ１２Ｂを形成し
、かつ、その窒化シリコン１ＩｉｌＯをマスクとして利
用しているため、高い自己整合性が得られ、高度な微細
加工を容易に行うことができる。Therefore, according to such a manufacturing method, openings 12A12B are selectively formed in the silicon nitride film 10 covering the silicon oxide film 6 formed on the surface of the silicon substrate 2, and the silicon nitride 1IilO is masked. Since it is used as a material, high self-alignment can be obtained and advanced microfabrication can be easily performed.
特に、第２図に示すように、レジストマスク２２の開口
部１４Ａ、１４Ｂが、窒化シリコン膜１０に形成した開
口部１２Ａ、１２Ｂからずれる場合でも、酸化シリコン
膜６のエンチングされる部分はｄｌｓｄＺの部分だけと
なり、自己整合性が損なわれることはない。In particular, as shown in FIG. 2, even if the openings 14A and 14B of the resist mask 22 are shifted from the openings 12A and 12B formed in the silicon nitride film 10, the etched portion of the silicon oxide film 6 is It becomes only a part, and self-consistency is not compromised.
また、窒化シリコン膜１０は極めて薄く形成できるので
、電極２４．２６０段切れを防止できるとともに、第１
図（Ｆ）に示すように、開口部１２Ａ、１２Ｂよりレジ
ストマスク２２に開口部１４Ａ１１４Ｂを大きく形成す
ることによって、酸化シリコン膜１８がオーバーハング
構造になることも防止できる。仮に、酸化シリコン膜６
．１８のサイドエツチングによって窒化シリコン膜１０
のみが残留してオーバーハング構造が生じても、酸化シ
リコンｌ！ｉｉ＋６′は極めて薄いため、それによる電
極２４．２６の段切れの問題は生じない。In addition, since the silicon nitride film 10 can be formed extremely thin, it is possible to prevent the electrode 24.260 from breaking, and the first
As shown in Figure (F), by forming the openings 14A and 114B in the resist mask 22 larger than the openings 12A and 12B, it is also possible to prevent the silicon oxide film 18 from forming an overhanging structure. If the silicon oxide film 6
．． By side etching 18, the silicon nitride film 10 is
Even if only silicon oxide remains and an overhang structure occurs, silicon oxide l! Since ii+6' is extremely thin, the problem of the electrodes 24, 26 being broken due to this does not occur.
なお、実施例では、エミッタ領域２０は、所定の不純物
をドープした多結晶シリコン層１６で開口部１２Ａを覆
い、熱拡散によって形成したが、開口部１２Ａに露出さ
せたベース領域４に、たとえばＮ形の不純物を直接熱拡
散法により、形成することもできる。In the embodiment, the emitter region 20 was formed by covering the opening 12A with the polycrystalline silicon layer 16 doped with a predetermined impurity and by thermal diffusion. A shaped impurity can also be formed by direct thermal diffusion.
以上説明したように、この発明によれば、高度な自己整
合性が実現できるので、微細パターンのどの微細加工を
要するものを効率的に製造することができ、その歩留り
を改善できるとともに、窒化膜のパンシベーション効果
によって信頼性の高い半導体装置を製造できる。As explained above, according to the present invention, it is possible to realize a high degree of self-alignment, so that it is possible to efficiently manufacture any micropattern that requires microfabrication, improve the yield, and improve the nitride film. Highly reliable semiconductor devices can be manufactured due to the pansivation effect.
施例を示す説明図、第２図はその自己整合性を示す説明
図である。An explanatory diagram showing an example, and FIG. 2 is an explanatory diagram showing its self-consistency.
、２・・・半導体基板、４・・・第１の導電領域として
のベース領域、６・・・絶縁膜としての酸化シリコン膜
、１０・・・窒化膜としての窒化シリコン膜、１２Ａ、
１２Ｂ、１４Ａ、１４Ｂ・・ （（・開口部、２０・・
・第２の導電領域としてのエミッタ領域。, 2... Semiconductor substrate, 4... Base region as first conductive region, 6... Silicon oxide film as insulating film, 10... Silicon nitride film as nitride film, 12A,
12B, 14A, 14B... ((・Opening, 20...
- Emitter region as second conductive region.
第１図 第１図 第１図 第２１！１Figure 1 Figure 1 Figure 1 21st!1
Claims (1)
した反対導電形の第１の導電領域を覆うように絶縁膜を
形成する工程と、この絶縁膜上に窒化膜を形成する工程
と、この窒化膜に前記第１の導電領域上の前記絶縁膜を
露出させる２以上の開口部を形成する工程と、これらの
開口部の内の１または２以上のものから前記絶縁膜を除
き前記第１の導電領域を露出させる工程と、この露出し
た第１の導電領域に反対導電形の第２の導電領域を形成
する工程と、この第２の導電領域を形成した部分以外の
開口部を介して前記絶縁膜を除き第１の導電領域を露出
させる電極形成用開口を形成する工程とからなることを
特徴とする半導体装置の製造方法。 （２） 前、記半導体基板はシリコンで形成し、前記絶
縁膜は酸化シリコンで形成し、前記窒化膜は窒化シリコ
ンで形成し、前記多結晶層はポリシリコンで形成したこ
とを特徴とする特許請求の範囲第１項に記載の半導体装
置の製造方法。[Claims] A step of forming an insulating film on a semiconductor substrate of ti>-conductivity type so as to cover a first conductive region of the opposite conductivity type formed on the surface layer thereof, and nitriding the insulating film on the insulating film. forming a film, forming two or more openings in the nitride film to expose the insulating film on the first conductive region, and forming one or more of these openings. a step of exposing the first conductive region by removing the insulating film, a step of forming a second conductive region of an opposite conductivity type in the exposed first conductive region, and a step of forming the second conductive region. 1. A method for manufacturing a semiconductor device, comprising the step of forming an electrode forming opening that exposes the first conductive region by removing the insulating film through the opening other than the portion of the insulating film. (2) The patent characterized in that the semiconductor substrate is made of silicon, the insulating film is made of silicon oxide, the nitride film is made of silicon nitride, and the polycrystalline layer is made of polysilicon. A method for manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7416084A JPS60218873A (en) | 1984-04-13 | 1984-04-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7416084A JPS60218873A (en) | 1984-04-13 | 1984-04-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60218873A true JPS60218873A (en) | 1985-11-01 |
Family
ID=13539122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7416084A Pending JPS60218873A (en) | 1984-04-13 | 1984-04-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60218873A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5056179A (en) * | 1973-09-13 | 1975-05-16 | ||
| JPS51127681A (en) * | 1975-04-30 | 1976-11-06 | Fujitsu Ltd | Manufacturing process of semiconductor device |
| JPS5488085A (en) * | 1977-12-26 | 1979-07-12 | Toshiba Corp | Nanufacture for semiconductor device |
| JPS5642367A (en) * | 1979-09-14 | 1981-04-20 | Toshiba Corp | Manufacture of bipolar integrated circuit |
| JPS5680162A (en) * | 1979-12-03 | 1981-07-01 | Ibm | Method of manufacturing pnp transistor |
| JPS57159055A (en) * | 1981-03-25 | 1982-10-01 | Toshiba Corp | Manufacture of semiconductor device |
-
1984
- 1984-04-13 JP JP7416084A patent/JPS60218873A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5056179A (en) * | 1973-09-13 | 1975-05-16 | ||
| JPS51127681A (en) * | 1975-04-30 | 1976-11-06 | Fujitsu Ltd | Manufacturing process of semiconductor device |
| JPS5488085A (en) * | 1977-12-26 | 1979-07-12 | Toshiba Corp | Nanufacture for semiconductor device |
| JPS5642367A (en) * | 1979-09-14 | 1981-04-20 | Toshiba Corp | Manufacture of bipolar integrated circuit |
| JPS5680162A (en) * | 1979-12-03 | 1981-07-01 | Ibm | Method of manufacturing pnp transistor |
| JPS57159055A (en) * | 1981-03-25 | 1982-10-01 | Toshiba Corp | Manufacture of semiconductor device |
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