JPS6020555A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6020555A JPS6020555A JP58127677A JP12767783A JPS6020555A JP S6020555 A JPS6020555 A JP S6020555A JP 58127677 A JP58127677 A JP 58127677A JP 12767783 A JP12767783 A JP 12767783A JP S6020555 A JPS6020555 A JP S6020555A
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- type
- substrate
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/114—PN junction isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は絶縁ゲート電界効果トランジスタおよび、これ
を含む集積回路構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to insulated gate field effect transistors and integrated circuit structures containing the same.
２重拡散形絶縁ゲート電界効果トランジスタ（以下ＭＯ
８ＦＥＴ と略記する）は、第１図に示すようにＸｐ形
基板１上に形成された低不純物濃度のｎ影領域２中に、
２重拡散によりｐ影領域３、ｎ影領域４を形成している
が、領域３はドレイ・ン領域２會取り囲み、しかも基板
１に到達する深さ以上に形成されている。ＭＯＳＦＥＴ
の高性能化は一般に短チヤネル化が知られているが、本
構造で短チヤネル化を実現すると、領域３の深さが浅く
なり、従ってｎ影領域２の厚さも薄くしなければならな
い。すなわち導電通路が狭くなることを意味し、直列抵
抗の増大を招く。またこのＭＯＳＦＥＴを集積回路素子
として使用する場合、薄い領域２は集積回路プロセスに
適合しない。Double diffused insulated gate field effect transistor (MO
8FET), as shown in FIG.
A p shadow region 3 and an n shadow region 4 are formed by double diffusion, and region 3 surrounds drain region 2 and is formed to a depth greater than that reaching substrate 1. MOSFET
It is generally known that the improvement in performance is achieved by shortening the channel. However, when shortening the channel with this structure, the depth of the region 3 becomes shallower, and therefore the thickness of the n-shaded region 2 must also be made thinner. This means that the conductive path becomes narrower, leading to an increase in series resistance. Also, when this MOSFET is used as an integrated circuit element, the thin region 2 is not compatible with the integrated circuit process.
本発明は前述の欠点を改善するためになされたもので、
直列抵抗の低減と、集積回路との整合性の改善を目的と
している。The present invention has been made to improve the above-mentioned drawbacks.
The purpose is to reduce series resistance and improve compatibility with integrated circuits.
本発明では上記目的を達成するために低不純物濃度領域
を厚くして、しかもドレイン領域を分離するための領域
を設けた構造を提供する。In order to achieve the above object, the present invention provides a structure in which the low impurity concentration region is thickened and a region for separating the drain region is provided.
第２図は本発明の実施例の断面構造を示すもので、ｎチ
ャネルの２重拡散形ＭＯ８ＦＥＴである。FIG. 2 shows a cross-sectional structure of an embodiment of the present invention, which is an n-channel double diffusion type MO8FET.
本装置の製造法を以下簡単に説明する。抵抗率２０Ω・
釧のｐ形基板１上の一部分にボロンを５Ｘ１０１５ケ／
ｃｒｎ２の割合でイオン注入した後、抵抗率１５Ω・α
の０層９を通常のエピタキシャル層によシ９μｍの厚さ
に形成する。引き続き通常の半導体プロセス技術により
、ｎ形層１１を４μｍの深さに、またｎ形層１２，１３
を２μｍの深さに拡散形成する。ｎ形層１１の形成は比
較的高温度の熱拡散なので、ｐ形層の形成と０層９のエ
ピタキシャル成長の両者の熱処理中にイオン注入された
ボロンが拡散されて、ｐ影領域１０を形成する。すなわ
ちエピタキシャル層９はｐ影領域１０および１１により
分離される。以下通常のＭＯ８ＦＥＴ製造プロセス４用
いて、１２０ ｎｍのゲート酸化膜１０１の形成、Ａｔ
によるソース、ゲート、ドレイン電極の形成などを行う
。第２図において１４，１５．１６は各々ゲート、ソー
ス、ドレイン電極、１００は酸化膜等の絶縁膜である。The manufacturing method of this device will be briefly explained below. Resistivity 20Ω・
Place 5 x 1015 pieces of boron on a part of the p-type substrate 1 of the chime.
After ion implantation at the rate of crn2, the resistivity is 15Ω・α
The 0 layer 9 is formed by a normal epitaxial layer to a thickness of 9 μm. Subsequently, using normal semiconductor process technology, the n-type layer 11 is formed to a depth of 4 μm, and the n-type layers 12 and 13 are formed.
is diffused to a depth of 2 μm. Since the n-type layer 11 is formed by thermal diffusion at a relatively high temperature, the boron ions implanted during the heat treatment for both the p-type layer formation and the epitaxial growth of the 0 layer 9 are diffused to form the p shadow region 10. . That is, epitaxial layer 9 is separated by p shadow regions 10 and 11. Below, using normal MO8FET manufacturing process 4, a 120 nm gate oxide film 101 is formed, At
Formation of source, gate, and drain electrodes, etc. In FIG. 2, 14, 15, and 16 are gate, source, and drain electrodes, respectively, and 100 is an insulating film such as an oxide film.
′本発明によればドレイン領域の分離を、基板中に埋込
まれた領域により行われている厚さ分だけ、低不純物濃
度層９を厚く出来、従って直列抵抗の改善を図ることが
できる。本発明の実施例では、同一寸法デバイスに対し
ｎ層の直列抵抗は約１／２となった。上記実施例ではド
レイン領域の分離は埋込み層により実現されたが、半導
体表面から他の拡散層により行うことも可能である。第
３図は本発明の他の実施例の断面構造を示したものであ
る。ｐ形層１上にｎ形エピタキシャル層１３（１ｍ９μ
ｍ形成する工程は第１の実施例と同一であるが、本実施
例ではエピタキシャル層形成後、高不純物濃度のｐ形打
抜き拡散層１７を形成する点が異っている。以下箱１の
実施例と同様のプロセスに従って、第３図に示した構造
のデバイスが実現された。直列抵抗の低減効果は第１の
実施例と同様である。第４図は本発明の他の実施例の断
面構造を示しだものである。本実施例の特徴は前記実施
例ではｎチャネル素子の場合、高抵抗率のｐ形基板を用
いてＭＯＳＦＥＴ を構成していた。従ってドレインと
基板間の容量成分は小さくなるが、直列抵抗成分は犬き
くなシ、高周波動作におけるドレイン損失の原因となる
。本実施例ではこのドレイン損失の低減を図るため、低
抵抗率のｐ形基板１８上に高抵抗率のｎ形層１９をエピ
タキシャル成長したウェーハを用いている。ｎ形層１９
の形成後は前記実施例と同一の工程で実施した。'According to the present invention, the low impurity concentration layer 9 can be made thicker by the thickness of the region buried in the substrate for separating the drain region, and therefore the series resistance can be improved. In the embodiment of the present invention, the series resistance of the n-layer was reduced to about 1/2 for a device of the same size. In the above embodiments, isolation of the drain region was achieved by a buried layer, but it can also be achieved by another diffusion layer from the semiconductor surface. FIG. 3 shows a cross-sectional structure of another embodiment of the present invention. N-type epitaxial layer 13 (1m9μ) on p-type layer 1
The step of forming m is the same as in the first embodiment, except that in this embodiment, after the epitaxial layer is formed, a p-type punched diffusion layer 17 with a high impurity concentration is formed. A device having the structure shown in FIG. 3 was realized following the same process as in the example in Box 1 below. The effect of reducing series resistance is the same as in the first embodiment. FIG. 4 shows a cross-sectional structure of another embodiment of the present invention. The feature of this embodiment is that in the previous embodiment, in the case of an n-channel device, a high resistivity p-type substrate was used to construct the MOSFET. Therefore, the capacitance component between the drain and the substrate becomes small, but the series resistance component remains and becomes a cause of drain loss in high frequency operation. In this embodiment, in order to reduce this drain loss, a wafer is used in which an n-type layer 19 of high resistivity is epitaxially grown on a p-type substrate 18 of low resistivity. n-type layer 19
After formation, the same steps as in the previous example were carried out.
第５図は本発明の他の実施例の断面構造を示したもので
ＭＯＳＦＥＴは、バイポーラトランジスタと集積化され
ている。すなわち高抵抗率ｐ形基板２０上に形成された
ｎ形層２１の厚さは、本発明によれば４μｍ〜３０μｍ
程度まで厚く形成できるので、従って通常のバイポーラ
トランジスタが容易に集積可能となる。以下第５図′の
実施例全簡単に説明する。高抵抗率ｐ形層２０の一部分
にアンチモン’に１２００Ｕで約１２時間拡散して埋込
み層２４を形成する。引き続きボロンを５×１５ケ／ｃ
ｒｎ２イオン注入した後ｎ層２１を９μｍの厚さにエピ
タキシャル成長する。以下アイソレーションめための９
層２３、コレクタ電極引出しのためのｎＪ’１ｉｉ３０
、ベースおよびチャネルを形成するための９層２５およ
び２６を４μｍの深さに拡散形成し、引き続きエミッタ
、ソースおよびドレインとなるｎ層２７．２８および２
９を２μｍの深さに拡散形成する。ゲート酸化膜および
電極の形成は第１の実施例と同一のプロセスに従って実
施した。以上述べたように、本実施例によれば、第１の
実施例で述べた直列抵抗を改善したＭＯＳＦＥＴを、従
来のバイポーラトランジスタと容易に集積化できること
が明らかである。FIG. 5 shows a cross-sectional structure of another embodiment of the present invention, in which the MOSFET is integrated with a bipolar transistor. That is, according to the present invention, the thickness of the n-type layer 21 formed on the high resistivity p-type substrate 20 is 4 μm to 30 μm.
Therefore, ordinary bipolar transistors can be easily integrated. The embodiment of FIG. 5' will be briefly described below. A buried layer 24 is formed in a portion of the high resistivity p-type layer 20 by diffusing antimony at 1200 U for about 12 hours. Continue to add 5 x 15 pieces of boron/c
After rn2 ion implantation, an n layer 21 is epitaxially grown to a thickness of 9 μm. Below is isolation meme 9
Layer 23, nJ'1ii30 for collector electrode extraction
, nine layers 25 and 26 to form the base and channel are diffused to a depth of 4 μm, followed by n-layers 27, 28 and 2 to form the emitter, source and drain.
9 is diffused and formed to a depth of 2 μm. The gate oxide film and electrodes were formed according to the same process as in the first example. As described above, according to this embodiment, it is clear that the MOSFET with improved series resistance described in the first embodiment can be easily integrated with a conventional bipolar transistor.
第６図は更に他の実施例を示したもので、本実施例では
、第５図に示したｐ形埋込み層２２を用いずに、高不純
物濃度のｉ曽３２をドレイン分離に用いている。この場
合ドレイン損失が増加しない様にチャネルを形成するた
めの１層３３と分離層３２とは隣接して形成されている
。またＭＯＳＦＥＴ のソースＳはバイポーラトランジ
スタのコレクタＣと接続されており、従って第７図に示
すような、カスコード回路を構成している。本構造にお
いても、バイポーラトランジスタとの集積化は容易であ
る。FIG. 6 shows still another embodiment. In this embodiment, the p-type buried layer 22 shown in FIG. 5 is not used, but an i-so layer 32 with a high impurity concentration is used for drain isolation. . In this case, the first layer 33 for forming a channel and the separation layer 32 are formed adjacent to each other so that drain loss does not increase. The source S of the MOSFET is connected to the collector C of the bipolar transistor, thus forming a cascode circuit as shown in FIG. Even in this structure, integration with bipolar transistors is easy.
以上述べたように、本発明によれば、ＭＯＳＦＥＴの直
列抵抗を低減でき、かつバイポーラトランジスタとの集
積化も容易である。As described above, according to the present invention, the series resistance of a MOSFET can be reduced, and integration with a bipolar transistor is also easy.
第１図は２重拡散形ＭＯ８ＦＥＴの断面構造を示す図、
第２図、第３図、第４図、第５図および第６図は各々本
発明の実施例の断面構造を示す図、第７図は本発明の実
施例の等価回路の一例を示す図である。
１・・・ｐ形基板、２・・・ｎ形層、３・・・ｐ形層、
４・・・ｎ形層、９・・・ｎ形層、１０・・・ｐ形層、
１７・・・ｐ形層、１８・・・高濃度ｐ形層、へ１９・
・・ｐ形層、２３・・・ｐ形層 １ 図
第２図
０１
■７図
０Figure 1 is a diagram showing the cross-sectional structure of a double diffusion type MO8FET,
2, 3, 4, 5, and 6 are diagrams each showing a cross-sectional structure of an embodiment of the present invention, and FIG. 7 is a diagram illustrating an example of an equivalent circuit of an embodiment of the present invention. It is. DESCRIPTION OF SYMBOLS 1...p-type substrate, 2...n-type layer, 3...p-type layer,
4...n-type layer, 9...n-type layer, 10...p-type layer,
17...p-type layer, 18...high concentration p-type layer, to 19.
...p-type layer, 23...p-type layer 1 Figure 2 Figure 01 ■7 Figure 0
Claims (1)
型を有する第１の領域と、第１の領域に形成された基体
と同−導電型金布する第２の領域の表面の一部に導電チ
ャネルを形成する絶縁ゲート形電界効果トランジスタに
おいて、第２の領域の厚さが、第１の領域の厚さよシも
小さく、かつ該絶縁ゲート電界効果トランジスタのドレ
イン領域が、第２領域と同一導電型を有する第３の領域
により他の領域よシ分離されていることを特徴とする半
導体装置。1. A first region formed on a semiconductor substrate of conductivity type and having a conductivity type opposite to that of the substrate, and a surface of a second region having the same conductivity type as the substrate formed in the first region. In an insulated gate field effect transistor in which a conductive channel is formed in the second region, the thickness of the second region is smaller than the thickness of the first region, and the drain region of the insulated gate field effect transistor is smaller than the thickness of the first region. A semiconductor device characterized in that the semiconductor device is separated from other regions by a third region having the same conductivity type as the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58127677A JPS6020555A (en) | 1983-07-15 | 1983-07-15 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58127677A JPS6020555A (en) | 1983-07-15 | 1983-07-15 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6020555A true JPS6020555A (en) | 1985-02-01 |
| JPH0433140B2 JPH0433140B2 (en) | 1992-06-02 |
Family
ID=14965978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58127677A Granted JPS6020555A (en) | 1983-07-15 | 1983-07-15 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020555A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0758228A (en) * | 1993-07-22 | 1995-03-03 | Philips Electron Nv | Integrated device |
-
1983
- 1983-07-15 JP JP58127677A patent/JPS6020555A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0758228A (en) * | 1993-07-22 | 1995-03-03 | Philips Electron Nv | Integrated device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0433140B2 (en) | 1992-06-02 |
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