JPS58218168A - Bidirectional transistor - Google Patents

Abstract

PURPOSE:To secure excellent and uniform characteristics with a relatively simple constitution by a method wherein a collector region, consisting of the second conductive type semiconductor, and an emitter region are provided in parallel with each other on one surface of the collector region, consisting of the first conductive type semiconductor substrate, maintaining the prescribed interval in transverse direction. CONSTITUTION:A P type low density resion (P<-> region) 101 is formed on the P type high density region (P<+> region) 100 located on a P type semiconductor substrate by performing vapor-phase growing method. In the P<-> region 101, the first N<+> region 102 and the second N<+> region 103 are formed maintaining the prescribed interval in transverse direction using a diffusion method. Above-mentioned P<+> region 100 and P<-> region 101 are corresponded to the base region as in transistor, the first N<-> region is corresponded to the collector region, and the second N<-> region 103 is corresponded to the emitter region respectively. As the emitter region and the collector region can be formed in complete simultaneousness from the same diffusion source on one surface of the first conductive type semiconductor substrate by performing the same thermal diffusion process, a transistor having genuine bidirectional characteristics can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a transistor having bidirectional characteristics, particularly a junction type transistor.

[Technical background of the invention and its problems]

An example of a conventional structure of a junction transistor (hereinafter referred to as a transistor) having bidirectional characteristics is shown in FIGS. 1 and 2.

In the transistor shown in FIG. 1, for example, an N-type high concentration semiconductor substrate (N+) is used as the collector region 1, and a relatively low concentration P-type region 3 (P-) is grown on the surface of the collector region 1 by vapor phase growth. is used as a base region, and a highly concentrated N-type region (N+) is formed in this P-type base region 3 by a selective diffusion method, and this is used as an emitter region 5, and the purpose is to make an ohmic contact in the P-type region 3. P-type region 4 (P
+). A metal wiring 7 made of Al or the like is provided in each base region 3 and emitter region 5 in ohmic contact. Reference numeral 6 indicates a thermal oxide film, and 2 indicates an N-type high concentration diffusion region (N+) for isolation.

The transistor shown in Fig. 1 has a current amplification factor h due to its structure.
It has the disadvantage that it is not possible to improve both the characteristics of fe and collector breakdown voltage.

That is, in the case of FIG. 1, when the respective concentrations of the collector region (N+) 1 and the P-type region (P-) 3 and the width of the base region 4 are controlled so that the current amplification factor hfe becomes 50 or more in both directions. Moreover, the collector breakdown voltage is only about 30 to 50V at most. This is because the depletion layer in the pace region 4 easily reaches the emitter region (N+) 1. On the other hand, although the collector breakdown voltage VCEO can be improved by increasing the base width, in that case the current amplification factor will decrease. In order to compensate for this decrease in current amplification factor, the emitter region (N+)
The impurity concentration of 5 may be made sufficiently large to improve the carrier injection efficiency.
If it exceeds atoms/cm3, lattice defects, dislocations, etc. will occur, making it impossible to obtain crystal perfection.

In addition, the high impurity concentration of the emitter region (N+) 5 itself shortens the lifetime of minority carriers injected from the base region (P+) 4 into the emitter region (N+) 5, so the diffusion distance of the minority carriers becomes short. As a result, the emitter injection efficiency cannot be increased beyond a certain level. For this reason, in the case of the transistor shown in Fig. 1, the current amplification factor is 50 to 100.
, a characteristic of collector breakdown voltage VCEO of about 30 to 50 V can only be expected.

Next, in the transistor shown in FIG. 2, for example, a highly doped N-type substrate (N+) is used as the collector region 8, and a relatively lightly doped N-type region 9 (N-) is grown on the surface of the collector region 9 by vapor phase growth. Furthermore, a relatively low concentration of P is applied to the surface of this N-type region 9.
A type region 10 (P-) is formed by impurity thermal diffusion, and a relatively low concentration N-type region 11 is formed on the surface of the P-type region 10.
(N-) is grown by a vapor phase growth method, and a highly concentrated N-type region 12 (N+) is further formed within the N-type region 11 by thermal diffusion or the like. Then, a P-type high concentration diffusion region 14 is formed in the N-type region 9 between the P-type region 10 and the thermal oxide film 13, and one of the P-type high concentration diffusion regions 14
A metal wiring 15 made of Al or the like is provided in ohmic contact to form a base electrode B. Further, the metal wiring 15 is also in ohmic contact with the N-type region 12 to form an emitter electrode E. Note that examples of the transistor shown in FIG.
902, and Japanese Patent Publication No. 57-2184.

The transistor shown in FIG. 2 has a potential barrier due to a concentration difference (N+, N-) in the emitter region, and minority carriers (11, 12) are injected from the base region 14 to the emitter region (11, 12) at a distance from the emitter base junction. In this case, it is formed at a position smaller than the diffusion distance of the hole (in this case). By adopting such a structure, it is possible to increase the emitter injection efficiency, and since the impurity concentration near the emitter base junction (N- part of 11) is low, it is possible to increase the collector breakdown voltage VCEO. 1
The drawbacks of the transistor shown in the figure can be overcome.

However, on the other hand, there are the following problems at the manufacturing stage.

That is, in the case of the transistor shown in FIG.
The N- region 11 above 0 must be formed by vapor phase growth. For example, if a thermal diffusion method is used for formation, the N- concentration is restricted by the necessity of inverting the P- impurity region, making it impossible to form a potential barrier. With the current vapor phase growth technology, the control accuracy of the thickness of the grown layer is about ±5%, and it is extremely difficult to form a potential barrier that requires fine adjustment. In addition, in the transistor shown in Fig. 2, the substrate on which the PN junction was formed by vapor phase growth (that is, the PN junction is formed by 10 and 9) was heated to 1200°C.
By performing thermal diffusion at the above high temperature, the N+ region 8 on the side surface or the P+ region 14 for taking out the base electrode B is formed, but at this time, impurities in the base region 10 are re-diffused, and the base width This causes the inconvenience of fluctuations. This means that good reproducibility of characteristics such as current amplification factor is poor.

Thus, in the case of the transistor shown in Fig. 2, the purpose is achieved as a bidirectional transistor with a high current amplification factor and a high collector breakdown voltage VCEO, but on the other hand, it lacks reproducibility and mass production, and is relatively expensive. becomes.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bidirectional transistor that has a high current amplification factor, a high collector breakdown voltage, has a relatively simple structure, has good and uniform characteristics, and is easy to manufacture.

[Summary of the invention]

In order to achieve the above object, a bidirectional transistor according to the present invention has a collector region and an emitter region made of a second conductivity type semiconductor on one side of a collector region made of a first conductivity type semiconductor substrate in a lateral direction (i.e., They are characterized in that they are provided in parallel at a predetermined interval in a direction (parallel to one surface of the first conductive type semiconductor substrate), and the base electrode is led out from the other surface side of the first conductive type semiconductor substrate.

〔Effect of the invention〕

According to the present invention having the above configuration, the emitter region and the collector region can be formed on one surface side of the first conductivity type semiconductor substrate at the same time and from the same impurity source by the same thermal diffusion process. A transistor having bidirectional characteristics can be constructed.

In addition, the width of the base region formed between the collector region and emitter region that are adjacent to each other can be determined by the distance between the collector region and emitter region, so the current amplification factor and breakdown voltage values can be optimized. It can be controlled arbitrarily and therefore good characteristics can be ensured. On the one hand, the degree of freedom in determining characteristics can be improved.

Furthermore, by adopting a structure in which the base electrode is led out from the other side of the first conductivity type semiconductor substrate, it is no longer necessary to provide metal wiring for taking out the base electrode on one side of the substrate, and as a result, one side of the substrate can be used as an emitter. It can be effectively used for forming a collector region.

In addition, from a manufacturing perspective, since the collector region and emitter region are provided in parallel on one side of the substrate, it is possible to use the diffusion method without using the conventional vapor phase growth method, and it is possible to achieve uniform It becomes possible to mass-produce bidirectional transistors with specific characteristics.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail based on illustrated embodiments.

First embodiment First embodiment of the present invention (NPN type)
is shown in Figure 4. In Fig. 4, P of the P-type semiconductor substrate is
A P-type low concentration region (hereinafter referred to as P− region) 101 is formed on a high concentration region 100 (hereinafter referred to as P+ region) by a vapor phase growth method. Within this P- region 101, there are two N-type high concentration regions (hereinafter, a first N+ region 102, a second N+ region 102, 103) is formed by a diffusion method. The above P+ region 100 and P− region 101 are the base regions of the transistor,
The first N- region 102 corresponds to a collector region, and the second N- region 103 corresponds to an emitter region.

A base electrode B is led out from the surface of the P+ region 100,
The first and second N-regions 102 and 103 each have Al
A collector electrode C and an emitter electrode E are provided, respectively.

Reference numeral 105 indicates a thermal oxide film.

Here, an example of the manufacturing process of the transistor according to the first embodiment will be summarized below.

(1) In a P-type substrate, a P- region 101 is formed on a P+ region 100 by vapor phase growth.

(2) Next, the substrate is subjected to steam oxidation treatment by exposing it to an oxidizing atmosphere at a temperature of 1000° C. for 1 hour and 20 minutes to grow a thermal oxide film 105.

(3) Next, a collector region (102) is formed on the thermal oxide film 105.
, an opening for forming an emitter region (103) is provided. The thermal oxide film 5 is removed by photoetching.

(4) Next, the first and second N+ regions 102° and 10° are formed by N-type impurity deposition through the openings, respectively.
form 3.

(5) Next, steam oxidation treatment is performed at a temperature of 1000° C. for 1 hour and 20 minutes.

(6) Next, diffusion is performed at a temperature of 1100° C. for 1 to 2 hours. At this time, the first and second N- regions 10
The impurities in 2 and 103 are re-diffused to adjust the distance between the two regions at the surface (ie, the base width) and control the current amplification factor of the transistor.

(7) Next, windows for extracting the collector electrode C and the emitter electrode E are opened in the thermal oxide film 105. The holes are made by photoetching.

(8) Next, metal 106 such as Al is placed in the opened part.
Deposit.

(9) Next, a part of the metal 106 is removed by photoetching,
A collector electrode 102 and an emitter electrode 103 are formed.

(10) Finally, a metal (Au, etc.) for extracting the base electrode B is vapor-deposited on the back surface of the P-type substrate.

Note that in the step (1) above, the P- region 101 is changed to P+.
Although P
A P+ region may be formed on the − region. In this case,
The so-called OSL wafer (One Side Lapped
Wafer) may also be used.

Note that there are methods for manufacturing junction transistors in bipolar integrated circuits that are similar to the junction transistor that enables lateral operation as in the present invention. An example is shown in FIG. However, in the case shown in FIG. 3, the N region forming the base region is formed on the same surface as the collector region and the emitter region, and the electrodes C, E, and B are all taken out from the same surface. Has a structure. In contrast, the structure of the present invention is derived from the other side, and its structure is clearly different. Moreover, while the device shown in FIG. 3 requires openings in the oxide film to lead out the base electrode, the device of the present invention does not require this. As a result, according to the structure of the present invention, one surface of the substrate can be used effectively and with a margin.

Second Embodiment A second embodiment of the present invention is shown in FIGS. 5, 6, and 7. In FIG. 5, FIG. 6, and FIG. 7, the same parts as in FIG. 4 are denoted by the same reference numerals, and the explanation thereof will be omitted.

First, the difference between the transistor according to the second embodiment and the transistor according to the first embodiment is that the first N- region 102
A P-type high concentration region (hereinafter referred to as a second P+ region) 107 exists between the second N- region 103 and the second N- region 103 . This second P+ region 107 is shown in FIGS.
Alternatively, it may be realized in the manner shown in FIG.

5 and 6, the first N+ region 102, the second
Each of the N+ regions 103 is a second region formed by diffusion.
It is formed so as to be covered by a P+ region 107. As a result, the second P+ region 107 is interposed in the base region 108 between the opposing surfaces of the first and second N+ regions 102 and 103. This second P+ region 107 suppresses the expansion of the depletion layer when a reverse bias is applied between the collector and emitter. Therefore, theoretically, the width or base width of the second P+ region 107 (FIG. 6a)
The wider is, the higher the withstand voltage VCEO is, but conversely the current amplification factor is lower. Therefore, by selecting the optimum value that satisfies both, it is possible to ensure good characteristics with a simple structure.

Here, an example of the manufacturing process of the transistor shown in FIGS. 5 and 6 will be summarized below.

(1) P− region 101 is grown on P+ region 100 by vapor phase growth.

(2) Steam oxidation treatment is performed by soaking the substrate at a temperature of 1000° C. for 1 hour and 20 minutes.

(3) Next, a diffusion hole is opened for forming an emitter region and a collector region. The holes are formed by removing the thermal oxide film by photoetching.

(4) P-type impurities are deposited within the P- region 101 to form two second P+ regions 107 at a predetermined interval.

(5) By depositing an N-type impurity in this second P+ region 107, the first and second ON+ regions 102,
103 are formed respectively.

(6) Next, it is immersed in an oxidizing atmosphere at a temperature of 1000° C. for 1 hour and 20 minutes to perform a steam oxidation treatment.

(7) Next, diffusion is performed at a temperature of 1100° C. for 1 to 2 hours. At this time, the first and second N- regions 102
, 103 to adjust the distance between both regions at the surface (ie, the base width a), and control the current amplification factor of the transistor.

(8) Next, windows for extracting the collector electrode C and the emitter electrode E are opened in the thermal oxide film 105. The holes are made by photoetching.

(9) Next, a metal 106 such as Al is deposited on the opened portion.

(10) Next, a portion of the metal 106 is removed by photoetching to form a collector electrode 102 and an emitter electrode 103.

(11) Finally, a metal (Au, etc.) for extracting the base electrode B is vapor-deposited on the back surface of the P-type substrate.

Note that in the step (1) above, the P- region 101 is changed to P+.
Although P
A P+ region may be formed on the − region. In this case,
The so-called OSL wafer (One Side Lapped
Wafer) may also be used.

Next, in FIG. 7, the second P+ region 107 is
It is provided in the middle of the pace area 108 between the + area 102 and the second N+ area 103 in the form of a partition wall. In this case as well, the second P+ region 107 has the function of suppressing the extension of the depletion layer and has the function of improving the withstand voltage.

Third Embodiment A third embodiment of the present invention is shown in FIG. The reference numerals of each part are those of the previous embodiment.

This transistor includes a first or second N+ region 102,
A second N+ region 109 and a channel stopper 110 are formed at the interface between P- region 101 and thermal oxide film 105 in a portion adjacent to region 103 to prevent generation of a channel due to surface inversion.

In this case, the channel stopper 110 is made by extending the P+ region 100, but a separate P+ region like the second N+ region 109 may be provided.

Although each of the embodiments shown above has been explained using an NPN transistor as an example, the structure of a PNP transistor is the same and falls within the technical scope of the present invention. Further, the P+ region 100 is provided because it is necessary to make ohmic contact for leading out the base electrode B on the back surface.

Further, in the second and third embodiments, the diffusion holes for forming the emitter region and the collector region are the same, but separate diffusion holes may be provided for diffusion. However, in that case, the width of the second P+ region 107 is equal to that of the emitter region 107.
It must be formed so that it is sufficiently smaller than the diffusion distance of minority carriers injected from No. 3.

Effects in each embodiment In each embodiment, the first and second N-regions 102, 1
03 are provided laterally in parallel with the substrate 100, and a base region 108 having an appropriate width is formed therebetween, so that a transistor with true bidirectional characteristics can be provided with uniform characteristics. .

Further, by adopting a structure in which the base electrode B is led out from the other side of the substrate 100, the following effects can be obtained. The transistor of the present invention has a substrate 10 as described above.
0, the base width 1 is the main element that determines the current amplification factor (IC/IB).
08 is a collector region (102) and an emitter region (10
3) is determined by the distance a between This base width is 108
changes to obtain the necessary current amplification factor depending on the impurity concentration of the emitter region (102) and collector region (103), etc., but in normal design, in order to obtain an amplification factor of several tens or more, the distance a should be 10 μm or less. There is a need to. Incidentally, the transistor shown in FIG. 6 is designed with a=5 μm. When trying to form a metal wiring for extracting the base electrode in such a narrow width, it is necessary to
Techniques for removing oxide films and metals with a width of several μm are required with an accuracy of m. However, achieving such precision is not easy with current optical etching technology. On the other hand, in order to increase the current amplification factor, it is preferable that the concentration in the base region be low, but in order to derive the base electrode, it is necessary to have a certain degree of concentration in the contact region due to the necessity of ohmic contact. Ru. In order to resolve such problems,
As shown in Fig. 3, it is also possible to form the base electrode B in a part other than the emitter region and between the collector regions on the same surface as the emitter and collector electrodes E and C, but in that case, the base region is the resistive component. This is undesirable because it acts as a barrier and interferes with the uniform operation of the device. Furthermore, in order to take out the base electrode B from the same surface, if a currently commonly used metal wire bonding method is used, it becomes necessary to separately form a bonding area (bonding pad). Providing this pounding pad is
The effective operating area of the board is limited by an amount corresponding to the area. Regarding this point, according to the lateral transistor structure shown in the present invention, the current capacity is determined by the circumferential length of the emitter region, and in order to obtain a large current capacity, it is necessary to increase the circumferential length of the emitter region. Although it is important to expand the effective operating area of the substrate and use it efficiently, the above-mentioned need can be satisfied by configuring the base electrode to be led out on the other side.

According to the second embodiment (FIGS. 5, 6, and 7), since the second P+ region 107 is formed in the base region 108 between the emitter region 103 and the collector region 102,
The growth of the depletion layer can be restricted, and as a result, the collector breakdown voltage (CEO) can be increased.

According to the third embodiment (FIG. 8), the channel stopper 1
By forming 10, P- region 101 and thermal oxide film 1
Since it is possible to prevent an inversion channel from occurring at the interface with 05,
Leakage current can be reduced, and therefore abnormal voltage drop defects can be prevented from occurring.

In addition, according to the bidirectional transistor according to the present invention (particularly the case shown in FIG. 5), the following characteristics were obtained.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views showing the structure of a conventional bidirectional transistor, FIG. 3 is a cross-sectional view showing a method of forming a transistor using a general bipolar integrated circuit, and FIG. 4 is a cross-sectional view showing a method of forming a transistor using a general bipolar integrated circuit. 5 is a sectional view showing the second embodiment, FIG. 6 is a perspective view of the bidirectional transistor in the second embodiment, and FIG. 7 is the second embodiment. FIG. 8 is a cross-sectional view showing a third embodiment of the second P+ region in a different manner. 100... P+ region in the substrate, 101... P- region in the substrate, 102... 1st N+ region (collector region), 103... 2nd N+ region (emitter region)
, B... base electrode, 107... second P+ region. Applicant's agent Kiyoshi Inomata

Claims (1)

[Scope of Claims] 1. A first region of a second conductivity type that becomes a collector region and a second region of a second conductivity type that becomes an emitter region are provided on one side of the first conductivity type semiconductor substrate that becomes a base region. The base electrodes are formed in parallel so as to be adjacent to each other at a predetermined interval in a direction parallel to the one surface of the first conductivity type semiconductor substrate, and base electrodes are led out from the other surface side of the first conductivity type semiconductor substrate. A bidirectional transistor characterized by: 2. In the device according to claim 1, between the first region of the second conductivity type and the second region of the second conductivity type, there is a semiconductor substrate of the first conductivity type having a higher concentration than the first conductivity type semiconductor substrate. A bidirectional transistor characterized by the presence of an impurity diffusion region. 3. In the device according to claim 2, the high concentration impurity diffusion region of the first conductivity type is formed to respectively cover the first and second regions of the second conductivity type in the semiconductor substrate of the first conductivity type. A bidirectional transistor characterized by being present between a first region and a second region of a second conductivity type. 4. In the device according to claim 2, the high concentration first conductivity type impurity diffusion region is arranged in the first conductivity type semiconductor substrate between the first conductivity type first region and the second conductivity type region. A bidirectional transistor characterized in that it is formed to have a depth equivalent to that of a layer in the first or second region, thereby existing between the first region and the second region of the second conductivity type.