[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS60147864A - Microcomputer device - Google Patents

Microcomputer device

Info

Publication number
JPS60147864A
JPS60147864A JP345084A JP345084A JPS60147864A JP S60147864 A JPS60147864 A JP S60147864A JP 345084 A JP345084 A JP 345084A JP 345084 A JP345084 A JP 345084A JP S60147864 A JPS60147864 A JP S60147864A
Authority
JP
Japan
Prior art keywords
information
bank
bank memory
cpu2
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP345084A
Other languages
Japanese (ja)
Inventor
Atsushi Yoshida
淳 吉田
Satoshi Shibuya
敏 渋谷
Kazushi Mizukami
水上　一志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP345084A priority Critical patent/JPS60147864A/en
Publication of JPS60147864A publication Critical patent/JPS60147864A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To efficiently perform information transmission between CPUs by using a memory, by providing the memory for temporarily storing information transmitted to the outside of the address space of each CPU. CONSTITUTION:When information is transmitted from the 1st CPU1 to the 2nd CPU2, the information is written in a bank memory 4 from the 1st CPU1 after bank change-over is made from the bank memory 4 for transmitting information to the main storage 12 of the 1st CPU1 by operating te bank memory control circuit 3 by means of a data bus 5 and address bus 7 and, after the writing is completed, the bank memory 4 is released from the 1st CPU1 by operating a bank memory control circuit 3. Then the 2nd CPU2 reads out the information from the bank memory 4 after making bank change-over from the bank memory 4 to the main storage 13 of the 2nd CPU2 by operating the bank memory control circuit 3 by means of a data bus 6 and address bus 8. After the information is read out, the CPU2 releases the bank memory 4 from the main storage 13 of the CPU2 by operating the bank memory control circuit 3 and performs information transmission from the 1st CPU1 to the 2nd CPU2.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、同一回路内に２個以上のＣＰＵを使用するマ
イクロコンピュータ装置ζこおいて、ＣＰＵ間の情報伝
達を効率よく行うことの可能なマイクロコンピュータ装
置に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is directed to a microcomputer device ζ that uses two or more CPUs in the same circuit, which is capable of efficiently transmitting information between the CPUs. It relates to a microcomputer device.

〔発明の背景〕[Background of the invention]

現状のマイクロコンピュータ装置では同一回路に２個υ
上のＣＰＵを使用する場合、バス調停用専用ＬＳＩを使
用したり、直列／並列による通信方式によりＣＰＵ間の
情報伝達を行っているが、これらの方式では情報伝達に
かなりの時間を要するため、システム全体の処理効率が
低下するという問題があった。In the current microcomputer equipment, there are two υ in the same circuit.
When using the above CPU, information is transmitted between the CPUs by using a dedicated LSI for bus arbitration or by serial/parallel communication methods, but these methods require a considerable amount of time to transmit information. There was a problem in that the processing efficiency of the entire system decreased.

〔発明の目的〕[Purpose of the invention]

本発明は、同一回路内に２個以上のＣＰＵｆ使用するマ
イクロコンピュータ装置のＣＰＵ間の情報伝達の処理効
率を向上するととζこより、システム全体の処理能力を
強化することを目的とする。An object of the present invention is to improve the processing efficiency of information transmission between the CPUs of a microcomputer device using two or more CPUs in the same circuit, and thereby to strengthen the processing capacity of the entire system.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため、本発明では各ＣＰＵのアドレ
ス空間外番と伝達される情報を一時格納しておくための
メモリを設け、このメモリをバンク切換えによりＣＰＵ
のアドレス空間内に割付は可能にすることによりＣＰ　
Ｕ間の情報伝達を効率よく行えるようにしたものである
。In order to achieve the above object, the present invention provides a memory for temporarily storing the address space outer number of each CPU and information to be transmitted, and this memory is transferred to the CPU by bank switching.
By allowing allocation within the address space of the CP
This allows for efficient information transmission between the U's.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図面に基づいて説明する。図
はＣＰＵを２個使用した場合の回路ブロック図で、１は
ＣＰＵＩ、２はＣＰＵ２゜３はバンクメモリ制御回路、
４は情報伝達用バンクメモリ、５は１のデータバス、６
は２のデータバス、７は１のアドレスバス、８は２のア
ドレスバス、９はバンクメモリ選択信号線、１０は４へ
のデータ線、１１は４へのアドレス線、１２は１の主記
憶メモリ、１３は２の主記憶メモリである。１から２へ
情報を伝達する場合、５と７により３を動作させ４を１
の主記憶にバンク切換えした後、１から４へ情報を書込
み、終了後３を動作させ４を１の主記憶から解放する。Hereinafter, one embodiment of the present invention will be described based on the drawings. The figure is a circuit block diagram when two CPUs are used, where 1 is the CPU, 2 is the CPU2, 3 is the bank memory control circuit,
4 is a bank memory for information transmission; 5 is a data bus of 1; 6
is the data bus of 2, 7 is the address bus of 1, 8 is the address bus of 2, 9 is the bank memory selection signal line, 10 is the data line to 4, 11 is the address line to 4, 12 is the main memory of 1 Memory 13 is the main memory of 2. When transmitting information from 1 to 2, 5 and 7 operate 3 and 4 becomes 1.
After bank switching to the main memory of 1, information is written from 1 to 4, and after completion, 3 is operated and 4 is released from the main memory of 1.

次に、２は６と８により３を動作させ４を２の主記憶に
バンク切換えし、４から情報を読出し、その後ろを動作
させ４を２の主記憶から解放し１から２への情報伝達を
行う３、 〔発明の効果〕 以上説明したように、本発明によれば特殊なＬＳＩ等を
使用することなく、ＣＰＵ間の情報伝達を効率よく行う
ことができる。Next, 2 operates 3 using 6 and 8, switches the bank of 4 to the main memory of 2, reads information from 4, operates the following, releases 4 from the main memory of 2, and transfers the information from 1 to 2. Transmission 3. [Effects of the Invention] As explained above, according to the present invention, information can be efficiently transmitted between CPUs without using a special LSI or the like.

【図面の簡単な説明】[Brief explanation of drawings]

図は同一回路内に２個のＣＰＵを使用した場合の本発明
の一実施例のブロック図である。 １・・・ＣＰＵ　１　２・・・ＣＰＵ２６・・・バンク
メモリ制御回路 ４・・・情報伝達用バンクメモリ ５・・・１のデータバス　６・・・２のデータバス７・
・・１のアドレスバス ８・・・２のアドレスバス ９・・・バンクメモリ選択信号線 １０・・・４へのデータ線　１１・・・４へのアドレス
線１２・・・１の主記憶メモリ １６・・・２の主記憶メモリThe figure is a block diagram of an embodiment of the present invention in which two CPUs are used in the same circuit. 1... CPU 1 2... CPU 26... Bank memory control circuit 4... Bank memory for information transmission 5... Data bus of 1 6... Data bus 7 of 2.
...Address bus 8 of 1...Address bus 9 of 2...Bank memory selection signal line 10...Data line to 4 Address line 12 to 11...4...Main memory of 1 16...2 main memory memory

Claims (1)

【特許請求の範囲】[Claims] １、同一回路内に２個以上のＣＰＵ（中央演算処理装置
）を使用するマイクロコンピュータ装置において、ある
ＣＰＵから他のＣＰＵへ情報を伝達する手段としてメモ
リ領域の一部をバンク切換えすることにより、この領域
をバッファ用メモリとして使用する手段を設け゛たこと
を特徴とするマイクロコンピュータ装置。1. In a microcomputer device that uses two or more CPUs (Central Processing Units) in the same circuit, by switching banks of a part of the memory area as a means of transmitting information from one CPU to another, A microcomputer device comprising means for using this area as a buffer memory.
JP345084A 1984-01-13 1984-01-13 Microcomputer device Pending JPS60147864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP345084A JPS60147864A (en) 1984-01-13 1984-01-13 Microcomputer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP345084A JPS60147864A (en) 1984-01-13 1984-01-13 Microcomputer device

Publications (1)

Publication Number Publication Date
JPS60147864A true JPS60147864A (en) 1985-08-03

Family

ID=11557667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP345084A Pending JPS60147864A (en) 1984-01-13 1984-01-13 Microcomputer device

Country Status (1)

Country Link
JP (1) JPS60147864A (en)

Similar Documents

Publication Publication Date Title
GB1572426A (en) Microcomputer systems including a memory
EP0067519B1 (en) Telecommunications system
JPS60147864A (en) Microcomputer device
JPH0238968B2 (en)
JPH0715670B2 (en) Data processing device
JPS6130300B2 (en)
JPS6217879Y2 (en)
JPH01291343A (en) Memory managing device
JPH03131951A (en) Data transfer system
JP2687679B2 (en) Program development equipment
JPS61233857A (en) Data transfer equipment
JP3106158B2 (en) Parallel computer equipment
JPS593665A (en) Multiaccessible memory system
JPS6061859A (en) Data communication system of microcomputer
JPS61153770A (en) Image processor
JPS6057095B2 (en) Storage device
JPS61120262A (en) Inter-memory intelligent dma controller
JPH01265354A (en) Data transfer system
JPS6175454A (en) Bus control system
JPS5836380B2 (en) Direct memory access method in multiprocessor systems
JPS62242264A (en) Communication controller
JPS6053901B2 (en) Inter-processor information transfer method
JPH01234962A (en) Bus control system
JPS58220542A (en) Data communication interface circuit
JPS60114927A (en) Film memory access control system