JPS6057095B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device that allows a plurality of processing units to be relatively tightly coupled in order to improve overall processing power.

Conventional techniques for relatively tightly coupling a processing device and a storage device include the following. (1) Channel-coupled type As shown in FIG. 1a, this is a system in which a set of processing units H, . . . Ho and storage devices 41, M2 are coupled by channels CH, . . . CH2.

A storage device M to which a certain processing device H or Ho belongs
, or ■When reading or writing to 40, channel CH,
, CH2, other processing devices, or storage devices. When a certain processing device H or Ho reads or writes to a storage device belonging to another processing device, it does so indirectly via the channel CH or CH2 using an input/output command.
The disadvantage of this approach is that when a large number of processing units and storage devices are combined, there is contention for the channels and storage by their own and other processing units' read and write operations.
(2) Bus-coupled type As shown in FIG.
This is a method of combining o.

Processing devices H, , Ho connect to storage devices M, , via bus B.
Read and write to Mo. The disadvantage of this scheme is that there is contention on bus B and storage devices M, .Mo by multiple processing units H, .H2.

(3) Multi-port combination type As shown in Figure 1c, entrances and exits (ports) for reading and writing of processing units H, , Ho and storage modules M, , Mo
This is a method in which a plurality of P's are connected to each other.

This method is physically and economically limited in the number of ports P, and is not suitable for combining a large number of processing units and storage devices.

Also, contention occurs in the storage device by multiple processing devices. A common drawback of each of the above-described coupling schemes is the competing demands of multiple processing units on the storage device.

The read and write requests issued by each processing device due to this contention form a queue. The processing device remains in a holding state until the storage device accepts the request and completes its operation. If the number of holding states increases, the overall processing capacity cannot be improved even if a plurality of processing devices are combined. As a method for reducing contention in storage devices, there is an improved multi-board memory using the combination method (3) above.

This storage device has a plurality of ports that accept requests, and consists of storage modules equal in number to the number of ports whose contents are always kept the same. For read requests, each storage module operates independently, so no contention occurs. However, in response to a write request, a write operation is performed on all storage modules at once in order to ensure that the contents of all storage modules match. Therefore, when write requests are issued by a plurality of processing devices, there is a drawback that contention occurs in the storage device. The present invention has been made in view of the above points, and reduces the rate at which processing units become stuck by reducing contention that occurs in a storage device that requires read and write operations from multiple processing units. This is designed to improve the overall processing capacity.

This invention will be explained below. FIG. 2 is a configuration diagram for explaining the principle of this invention.

In FIG. 2, 10, 20, 30 are processing units,
Storage modules 11, 12, 21, 22, 31, and 32 accept only requests for read operations from the processing devices 10, 20, and 30, respectively. Yule 113, 23, 33 are storage modules 14, 15, 24, which accept requests for read and write operations of the processing devices 10, 20, 30;
25, 34, and 35 are the storage modules 11 and 35, respectively.
Storage module control circuits 12, 21, 22, 31, and 32 are paired with each other, and storage module control circuits 16, 26, and 36 are paired with the storage modules 13, 23, and 33, respectively. As described above, the present invention provides the processing device 10
a storage module 13 that accepts read and write operation requests; a storage module control circuit 16 that sends out information corresponding to the write operation requests; and a plurality of storage modules 11 and 12 that accept only read operation requests from the processing device 10. Based on the information sent from other storage module control circuits, the storage module 11
, 12, the storage module control circuit 14 rewrites the contents of
. Here, the information corresponding to the write operation request is mainly the memory address and the content to be written.

In the storage device of the present invention, for example, a storage module 13 that accepts requests for read and write operations and a storage module control circuit 16 that sends information corresponding to requests for write operations are paired. Furthermore, storage modules 11 and 12 that accept only requests for read operations and storage module control circuits 14 and 15 that rewrite the contents of the storage modules 11 and 12 are also paired. There may be any number of storage modules, such as 11, 12, etc., to which one processing device 10 can directly issue a request for a read operation. Next, the operation of each part of each of the storage devices will be explained, focusing mainly on the relationship with the processing device 10.

The processing device 10 sends a request for a read operation to the storage module 1.
It can be played on numbers 1, 12, and 13.

On the other hand, a request for a write operation can be issued only to the storage module 13. When the processing device 1 requests a write operation to the storage module 13, the contents of the corresponding address are rewritten using the storage address and the content to be written issued from the processing device 10 accompanying the request.
At the same time, these storage addresses and the contents to be written are sent by the storage module control circuit 16 to storage module control circuits 24 and 35 belonging to other processing devices. At this time, the storage module control circuit 16 is connected to the storage module control circuit 2.
Information is unilaterally sent regardless of the status of 4 and 35.
The storage module control circuits 14 and 15 are connected to a storage module control circuit 36 that is connected to a storage module that is permitted to receive write operation requests belonging to other processing devices.
, 26, and rewrites the contents of the storage modules 11, 12 using the information. The storage device as a whole operates as follows.

All parts of the storage device start operating all at once from a stopped state, and immediately after the start of operation, each processing device 10, 20, 30 connects the storage module 13, 23, 33 to which write operations are permitted from the processing device. Assume that the initial values at all addresses are written. This operation is performed by the storage module 13.
, 23, 33, so
The storage module control circuits 16, 26, 36 (16→
24, 16 → 35, 26 → 15, 36 → 14), the storage modules 21, 32, 12, 11 to which only read operations are allowed from the processing devices 10, 20, 30
The contents of are also rewritten to the same value. Each processing device 10, 2
When the write operations for all addresses 0 and 30 are completed, the contents of all addresses of all storage modules are set to initial values. After that, each of the processing units 10, 20, and 30 continues its own processing, but if there is a request for a write operation to the storage device during that processing, the storage device will store data in a storage module that is permitted to perform the write operation. The contents of a storage module connected through the module control circuit and only permitted to read from the processing device are also rewritten to the same value. That is,
Storage modules 13, 23 that allow write operations
, 33 and storage module control circuits 16, 26, 3
The storage modules (21 and 32 for 13, 12 for 23, 11 for 33) connected through 6 and which are only allowed for read operations will have exactly the same content. With this configuration, when the processing device 10 needs the information written in the storage module 23 of the processing device 20, it can achieve the purpose by issuing the request to the storage module 12 without requesting the storage module 23 to perform a read operation. can be achieved.

In this case, since the processing device 10 is the only device that requests a read operation from the storage module 12, no conflict occurs due to requests for read operations. Further, since the operation of the storage module control circuit 16 is influenced only by the request for a write operation to the storage module 13 of the processing device 10, the requests for read and write operations to the storage module 13 of the processing device 10 are affected by other processing devices. 20,3
Accepted regardless of 0 requests. That is, no contention occurs due to requests for read and write operations. Another type of conflict is a conflict between a request for a rewrite operation on the storage module 11 by the storage module control circuit 14 and a request for a read operation on the storage module 11 from the processing device 10 .

To deal with this, it is only necessary to arbitrate between the two requests from the storage module control circuit 14 and the processing device 10, so the influence of competition can be reduced by increasing the operating speed of the storage module 11 to a certain extent using statistical knowledge. Is possible. FIG. 3 is a block diagram showing one embodiment of the present invention.

In this figure, 40 is a processing device, 41 is a storage module that only accepts read operation requests from the processing device 40, and 42 is a storage module that accepts read and write operation requests from the processing device 40.
These 40, 41, 42 are, for example, 10, 11 in FIG.
, 13. 43 and 44 are first in, first out (FIF
O) registers, 45 and 46 are serial/parallel conversion registers,
Reference numeral 47 denotes a communication path connected to a storage control circuit of a storage module that accepts requests for write operations belonging to other processing devices.

Then, the serial data from the communication path 47 is converted into parallel data by the serial/parallel conversion registers 45 and 46, and
is stored in 48 and 49 are FIFQ type registers, 5
0 and 51 are parallel-to-serial conversion registers that convert parallel data from the registers 48 and 49 into serial, and 52 is a communication connected to a storage module control circuit of a storage module that accepts only requests for read operations belonging to other processing devices. 53 is an address bus, and 54 is a data bus.

Information from the address bus 53 and data bus 54 is stored in registers 48 and 49, and the parallel data read therefrom is converted into serial data by parallel-to-serial conversion registers 50 and 51 and output to a communication path 52. A multiplexer 55 switches the contents of the address bus 53 and the contents of the register 43.

Next, the operation will be explained.

The processing device 40 puts an address on the address bus 53 when requesting a read operation to the storage device, and puts an address on the address bus 53 and data on the data bus 54 when requesting a write operation.

When the address requested for a read operation indicates the storage module 42, the storage module 42 outputs the contents of the corresponding address to the data bus 54. When the address requested for a read operation indicates the storage module 41, if the registers 43 and 44 are empty, the storage module 41 outputs the contents of the corresponding address to the data bus 54. If the registers 43 and 44 are not empty, the read operation request is suspended and the registers 43 and 44 are
The storage module 41 performs the rewriting operation until the memory becomes empty. At this time, the multiplexer 55 is switched to the register 43 side, and the contents of the register 43 are rewritten as the address of the storage module 41 and the contents of the register 44 are rewritten as the data of the storage module 41. When processing device 40 issues a write operation to storage module 42, storage module 4
2 uses the contents of the address bus 53 as an address, and the data bus 5
A write operation is performed using the contents of 4 as data.

At the same time, registers 48 and 49 are connected to address bus 53, respectively.
, , stores the contents of the data bus 54. Parallel-serial conversion registers 50 and 51 convert any information in registers 48 and 49 into serial data and send it to communication path 52. On the other hand, serial-to-parallel conversion registers 45 and 46 convert the serial data from communication path 47 into parallel data, and store the data in registers 43 and 44, respectively. The communication capacity of the communication channels 47 and 52 may be smaller than the value commensurate with the processing speed of the processing device 40.

This is because the processing device 40 does not continue to request only write operations to the storage device. This means that the communication channels 47 and 52 can be realized by means that are physically and economically easy, and is advantageous for coupling a large number of processing devices. By connecting the necessary number of each element shown in FIG. 3, it is possible to create a compound computer with less contention in the storage device. As explained in detail above, in a storage device having a plurality of processing devices, the present invention provides for each processing device to
A storage module that accepts requests for read and write operations, a storage module control circuit that controls this, and a plurality of storage modules that accept only requests for read operations;
The storage module control circuits that control this are set as one set, and the storage module control circuit of the storage module accepts requests for read and write operations in one group, and the storage module control circuit of the storage module accepts only requests for read operations in the other group. Since the circuits are interconnected, when multiple processing units and storage devices are combined, the rate at which requests for read and write operations by the processing units compete with each other on the storage device is reduced to a level that does not pose a practical problem. This has the advantage that the processing capacity of the processing device can be efficiently utilized.

[Brief explanation of the drawing]

Figures 1A, b, and c are diagrams showing various methods of connecting conventional processing devices and storage devices, Figure 2 is a block diagram showing the principle of the present invention, and Figure 3 is an embodiment of the present invention. There is a configuration diagram showing this. In the figure, 10, 20, 30 are processing devices, 11, 12, 21
, 22, 31, and 32 are storage modules that accept only requests for read operations; 13, 23, and 33 are storage modules that accept requests for read and write operations; 14-
16, 24-26, 34-36 are storage module control circuits.

Claims (1)

[Claims] 1. In a storage device in which read and write operations are requested from a plurality of processing devices, a storage module that accepts requests for read and write operations from the processing devices and sends information corresponding to requests for write operations to this storage module. A storage module control circuit, a plurality of storage modules that accept only read operation requests from the processing device, and a storage module control circuit that controls the plurality of storage modules are set as one set, and these are provided in the same number as the processing devices. , further comprising a storage module control circuit of a storage module that accepts requests for read and write operations in a certain group, a storage module control circuit of a storage module that accepts only requests for read operations in another group, and a storage module control circuit of a storage module that accepts requests for read operations in another group; A storage device characterized in that a storage module control circuit of a storage module that accepts only requests is interconnected.