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JPS60133739A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60133739A
JPS60133739A JP24131383A JP24131383A JPS60133739A JP S60133739 A JPS60133739 A JP S60133739A JP 24131383 A JP24131383 A JP 24131383A JP 24131383 A JP24131383 A JP 24131383A JP S60133739 A JPS60133739 A JP S60133739A
Authority
JP
Japan
Prior art keywords
groove
film
substrate
epitaxial layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24131383A
Other languages
Japanese (ja)
Inventor
Atsushi Sudo
淳 須藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24131383A priority Critical patent/JPS60133739A/en
Publication of JPS60133739A publication Critical patent/JPS60133739A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To flatten the surface without bird beak by forming U-shaped sectional groove in a substrate, coating the side of the groove with oxidation resistant film, then forming an epitaxial layer in the groove, and oxidizing the surface as an element separating region. CONSTITUTION:With a resist film 4 as a mask an Si3N4 film 3, an SiO2 film 2 and a substrate 1 are etched by reactive ion etching (RIE), and a groove 5 of U-shaped section is formed in the substrate 1. Then, an SiO2 film 7 is formed only in the bottom 5'. Then, an Si3N4 film 8 is formed only on the side of the groove 7. Thereafter, an epitaxial layer 9 is formed in the groove 7. Then, the layer 9 is oxidized to form an SiO2 film. Subsequently, the film 2 is removed by cutting to form an element separating region 11 and an element region 12.

Description

【発明の詳細な説明】 （ａ）　発明の技術分野 本発明は半導体装置の製造方法、特に集積回路の素子分
離領域の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an isolation region of an integrated circuit.

（ｂ）　従来技術と問題点 従来半導体集積回路における素子間の分離は半導体基体
を選択的に酸化（７て得られた厚い酸化膜を用いる構造
があるが、このような素子分離領域を形成する場合、パ
ターニングされた耐酸化膜、例えば窒化硅素（８１３Ｎ
４　）の下に酸化膜（Ｓｔｏｗ）が入りこむ、いわゆる
バーズ・ピークが生じ、微細パターンの形成に障害とな
っていた。(b) Conventional technology and problems Conventionally, isolation between elements in semiconductor integrated circuits is achieved by selectively oxidizing the semiconductor substrate (7). In some cases, a patterned oxidation-resistant film, such as silicon nitride (813N
4) A so-called bird's peak, in which an oxide film (Stow) enters under the pattern, occurs and becomes an obstacle to the formation of fine patterns.

また厚い酸化膜は、その厚さのおよそ半分を半導体基体
表面上に露出するので基体表面に凸凹が生じ、これが配
線の断線の要因となっていた。Furthermore, since approximately half of the thickness of the thick oxide film is exposed on the surface of the semiconductor substrate, unevenness occurs on the surface of the substrate, which causes disconnection of wiring.

（ｃ）　発明の目的 本発明は、従来のこのような欠点を解消し、バーズビー
クを生じることなく表面が平担な素子分離領域を形成す
る方法を提供することを目的とする。(c) Object of the Invention It is an object of the present invention to provide a method for eliminating such conventional drawbacks and forming an element isolation region with a flat surface without producing a bird's beak.

（ｄ）　発明の構成 上記目的を達成するための本発明は、半導体基体に断面
形状Ｕ字形の溝を形成し、該溝の底面を除いて側面を耐
酸化膜で覆った後、該溝内にエピタキシャル層ヲ形成り
、、次いで該エピタキシャル１−を酸化し、該酸化され
た領緘を素子分離領域とすることを特徴とする。(d) Structure of the Invention To achieve the above object, the present invention forms a groove having a U-shaped cross section in a semiconductor substrate, covers the side surfaces of the groove except for the bottom surface with an oxidation-resistant film, and then The method is characterized in that an epitaxial layer is formed on the substrate, and then the epitaxial layer 1- is oxidized, and the oxidized region is used as an element isolation region.

（ｅ）　発明の実施例 以下、図面を用いて本発明の一実施例を説明する。(e) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

まず第１図に示すように、シリコン基板１上に二酸化硅
素（８１０２）膜２．窒化硅素（ｓｔｓＮ＋）　Ｈ３を
形成する。First, as shown in FIG. 1, a silicon dioxide (8102) film 2. Form silicon nitride (stsN+) H3.

次に第２図に示すように、レジスト膜４をバターニング
形成後、これをマスクにしてリアクティブ・イオン・エ
ツチング（ＲＩＥ）によりＳｉ３Ｎ、膜３　、　ｓｔｏ
ｗ膜２．基板１をエツチングし、基板１に対して断面形
状がＵ字形の溝５を形成する。Next, as shown in FIG. 2, after patterning the resist film 4, using this as a mask, reactive ion etching (RIE) is performed to pattern Si3N, film 3, and sto.
w membrane 2. The substrate 1 is etched to form a groove 5 having a U-shaped cross section.

次に第３図に示すようにレジストを除去した後酸素イオ
ン６を溝５の底部５′に注入し、５ｉＯｚ膜７を底部５
′のみに形成する。Next, as shown in FIG. 3, after removing the resist, oxygen ions 6 are injected into the bottom 5' of the trench 5, and a 5iOz film 7 is formed at the bottom 5'.
′ only.

次いで９素雰囲気中で加熱することにより、第４図に示
すように溝７の側面のみＫＳｉ、Ｎ、膜８を形成する。Next, by heating in a 9 element atmosphere, a KSi, N, film 8 is formed only on the side surfaces of the groove 7, as shown in FIG.

次に選択エピタキシャル成長により、第５図に示すよう
に溝７内にエピタキシャル層９を形成する。Next, an epitaxial layer 9 is formed in the groove 7 by selective epitaxial growth, as shown in FIG.

次に熱酸化を行い、第６図に示すように溝７内のエピタ
キシャル層を酸化し、５ｌＯ７層１ｏを形成する０ 次に８１０□膜２を除去するまで削ると、第７図に示す
ように素子外Ａｆｆｅ領域１１と素子領域１２とが形成
される。Next, thermal oxidation is performed to oxidize the epitaxial layer in the groove 7 as shown in FIG. 6, forming a 5lO7 layer 1o. An extra-element Affe region 11 and an element region 12 are formed.

この後素子領域１２に不純物の導入等、通常の工程を用
いて素子を形成する。Thereafter, an element is formed using normal processes such as introducing impurities into the element region 12.

（ｆ）発明の詳細 な説明した通り、本発明によればバーズピーりがなく、
シかも表面が平担な素子分離領域が形成され、従って、
高集積化と共に歩留りの向上が図られる。(f) As described in detail, according to the present invention, there is no bird's pee.
Furthermore, an element isolation region with a flat surface is formed, and therefore,
The yield can be improved with higher integration.

【図面の簡単な説明】[Brief explanation of the drawing]

図において、１はシリコン基板、２．７．１０は二酸化
硅素、３，８け窒化硅素、１１は素子分離領域、１２は
素子領域を示す。 ３− ４−In the figure, 1 is a silicon substrate, 2, 7, 10 is silicon dioxide, 3,8 silicon nitride, 11 is an element isolation region, and 12 is an element region. 3- 4-

Claims (1)

【特許請求の範囲】[Claims] 半導体基体に断面形状Ｕ字形の溝を形成し、該溝の底面
を除いて側面を耐酸化膜で覆った後、該溝内にエピタキ
シャル層を形成し、次いで該エピタキシャル層を酸化し
、該酸化された領域を素子分離領域とすることを特徴と
する半導体装置の製造方法。After forming a groove with a U-shaped cross section in a semiconductor substrate and covering the side surfaces of the groove except for the bottom surface with an oxidation-resistant film, an epitaxial layer is formed in the groove, and then the epitaxial layer is oxidized. A method for manufacturing a semiconductor device, characterized in that the region formed by the separation is used as an element isolation region.
JP24131383A 1983-12-21 1983-12-21 Manufacture of semiconductor device Pending JPS60133739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24131383A JPS60133739A (en) 1983-12-21 1983-12-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24131383A JPS60133739A (en) 1983-12-21 1983-12-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60133739A true JPS60133739A (en) 1985-07-16

Family

ID=17072430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24131383A Pending JPS60133739A (en) 1983-12-21 1983-12-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60133739A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5108946A (en) * 1989-05-19 1992-04-28 Motorola, Inc. Method of forming planar isolation regions
US5126288A (en) * 1990-02-23 1992-06-30 Rohm Co., Ltd. Fine processing method using oblique metal deposition
US5457067A (en) * 1993-10-14 1995-10-10 Goldstar Electron Co., Ltd. Process for formation of an isolating layer for a semiconductor device
US5661073A (en) * 1995-08-11 1997-08-26 Micron Technology, Inc. Method for forming field oxide having uniform thickness
DE4441542B4 (en) * 1993-11-26 2007-09-20 Denso Corp., Kariya SOI semiconductor device with island regions and method for their production

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5108946A (en) * 1989-05-19 1992-04-28 Motorola, Inc. Method of forming planar isolation regions
US5126288A (en) * 1990-02-23 1992-06-30 Rohm Co., Ltd. Fine processing method using oblique metal deposition
US5457067A (en) * 1993-10-14 1995-10-10 Goldstar Electron Co., Ltd. Process for formation of an isolating layer for a semiconductor device
DE4441542B4 (en) * 1993-11-26 2007-09-20 Denso Corp., Kariya SOI semiconductor device with island regions and method for their production
DE4441542B8 (en) * 1993-11-26 2008-05-29 Denso Corp., Kariya SOI semiconductor device with island regions and method for their production
US5661073A (en) * 1995-08-11 1997-08-26 Micron Technology, Inc. Method for forming field oxide having uniform thickness
US6103595A (en) * 1995-08-11 2000-08-15 Micron Technology, Inc. Assisted local oxidation of silicon

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