JPH01244636A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01244636A JPH01244636A JP7227888A JP7227888A JPH01244636A JP H01244636 A JPH01244636 A JP H01244636A JP 7227888 A JP7227888 A JP 7227888A JP 7227888 A JP7227888 A JP 7227888A JP H01244636 A JPH01244636 A JP H01244636A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- trench
- silicon
- silicon nitride
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000002253 acid Substances 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 238000010276 construction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に素子間を酸化物によ
り電気的に分離する工程を含む半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a step of electrically isolating elements using oxide.
半導体装置における素子間酸化膜分離の一方法として、
シリコン半導体基板上に第1耐酸化性膜を設け、分離領
域に対応する領域の第1耐酸化性膜を除去し、このシリ
コン半導体基板に少なくとも部分的に前記第1耐酸化性
膜の下方に延在する側壁を有する溝を形成し、この後前
記の第1耐酸化性膜に隣接した第2耐酸化性膜を前記の
溝上に設けてから、シリコン半導体基板に酸化処理を施
す方法がある。As a method for separating oxide films between elements in semiconductor devices,
A first oxidation-resistant film is provided on a silicon semiconductor substrate, and the first oxidation-resistant film in a region corresponding to the isolation region is removed, and at least a portion of the first oxidation-resistant film is provided below the first oxidation-resistant film on the silicon semiconductor substrate. There is a method in which a trench having an extending sidewall is formed, a second oxidation-resistant film adjacent to the first oxidation-resistant film is provided on the trench, and then the silicon semiconductor substrate is subjected to oxidation treatment. .
第2図(a)〜(e)は従来の半導体装置の素子分離方
法の一例を説明するための工程順に示した半導体チップ
の断面図である。FIGS. 2(a) to 2(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for separating elements of a semiconductor device.
まず、第2図(a>に示すように、シリコン基板1の主
表面に酸化シリコン膜2を10〜1100nの厚さに成
長させ、この酸化シリコン膜2上に窒化シリコン膜3を
10〜300nmの厚さに堆積する。ホトリソグラフィ
技術により窒化シリコン膜3及び酸化シリコン膜2を選
択的にエツチングし、開孔部4を形成して、シリコン基
板1の分離領域に対応する領域の主表面を選択的に露出
させる。First, as shown in FIG. 2 (a), a silicon oxide film 2 is grown on the main surface of a silicon substrate 1 to a thickness of 10 to 1100 nm, and a silicon nitride film 3 is grown on the silicon oxide film 2 to a thickness of 10 to 300 nm. The silicon nitride film 3 and silicon oxide film 2 are selectively etched using photolithography technology to form openings 4, and the main surface of the silicon substrate 1 in the region corresponding to the isolation region is etched. selectively exposed.
次に、第2図(b)に示すように、開孔部4により露出
されたシリコン基板1の主表面を、窒化シリコン膜3及
び酸化シリコン膜2をマスクとして、等方性蝕刻法によ
り除去し、湧5を形成する。Next, as shown in FIG. 2(b), the main surface of the silicon substrate 1 exposed through the opening 4 is removed by isotropic etching using the silicon nitride film 3 and the silicon oxide film 2 as masks. Then, spring 5 is formed.
次に、第2図(c)に示すように、消5の表面を酸化し
て酸化シリコン膜6を10〜1100nの厚さに成長さ
せ、更にその上に窒化シリコン膜7を10〜300nm
の厚さに堆積する。このとき、窒化シリコン膜7は、溝
5の底面及び側面の酸化シリコン膜6上に堆積され、ま
た溝5の上面に突き出た「ひさし」の周囲にも形成され
る。Next, as shown in FIG. 2(c), the surface of the eraser 5 is oxidized to grow a silicon oxide film 6 to a thickness of 10 to 1100 nm, and a silicon nitride film 7 is further formed thereon to a thickness of 10 to 300 nm.
Deposited to a thickness of . At this time, the silicon nitride film 7 is deposited on the silicon oxide film 6 on the bottom and side surfaces of the trench 5, and is also formed around the "eaves" protruding from the top surface of the trench 5.
次に、第2図(d)に示すように、講5の上面に突き出
た[ひさしJをマスクとして、溝5の底面に堆積された
窒化シリコン膜7を異方性蝕刻法により除去し、開孔部
8を形成する。従って満5の側面には窒化シリコン膜7
が残った状態となる。Next, as shown in FIG. 2(d), the silicon nitride film 7 deposited on the bottom surface of the groove 5 is removed by anisotropic etching using the eaves J protruding from the top surface of the groove 5 as a mask. An opening 8 is formed. Therefore, the silicon nitride film 7
remains.
次に、第2図(e)に示すように窒化シリコン3及び7
をマスクとして酸化処理を施して素子間分離酸化膜10
を形成する。Next, as shown in FIG. 2(e), silicon nitride 3 and 7
The element isolation oxide film 10 is formed by performing oxidation treatment using the mask as a mask.
form.
上述した方法によって形成された素子間分離酸化膜は、
溝の側面に窒化シリコン膜7を堆積させない場合よりも
、酸化膜の構法がりが小さくなる。しかし、特に厚い素
子間分離酸化膜になると、厚さに比例して構法がりが大
きくなるため、分離領域の低減ができないという欠点が
あった。The device isolation oxide film formed by the method described above is
The structure of the oxide film becomes smaller than when the silicon nitride film 7 is not deposited on the side surfaces of the trench. However, when a particularly thick element isolation oxide film is used, the structure has a disadvantage that the isolation region cannot be reduced because the structure becomes larger in proportion to the thickness.
本発明の半導体装置の製造方法は、半導体基板に形成し
ようとする素子分離領域に第1の開孔部を有する第1の
耐酸化性膜を形成する工程と、前記第1の耐酸化性膜を
マスクにして前記半導体基板を等方性エツチングして前
記開孔部より広い第1の溝を形成する工程と、前記第1
の溝の表面を覆う第2の耐酸化性膜を形成する工程と、
前記第1の講の底面上の前記第2の耐酸化性膜に前記第
1の開孔部に対応する第2の開孔部を形成して前記半導
体基板の表面を露出させる工程と、前記第1及び第2の
耐酸化性膜をマスクとして前記第1の溝の底面を異方性
エツチングして第2の溝を形成する工程と、前記第1及
び第2の耐酸性膜をマスクとして酸化を行う工程とを含
んで構成されろ。The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a first oxidation-resistant film having a first opening in an element isolation region to be formed in a semiconductor substrate; isotropically etching the semiconductor substrate using a mask as a mask to form a first groove wider than the opening;
forming a second oxidation-resistant film covering the surface of the groove;
forming a second opening corresponding to the first opening in the second oxidation-resistant film on the bottom surface of the first hole to expose the surface of the semiconductor substrate; forming a second groove by anisotropically etching the bottom surface of the first groove using first and second oxidation-resistant films as masks; and using first and second acid-resistant films as masks to form a second groove. and a step of performing oxidation.
[実施例〕
次に、本発明の実施例について図面を参照して説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.
第1図(a)〜(f)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
まず、第1図(a)に示すように、シリコン基板1の主
表面に、酸化シリコン膜2を10〜1100nの厚さに
成長させ、この酸化シリコン膜2上に窒化シリコン膜3
を10〜300nmの厚さに堆積し、ホトリソグラフィ
技術を用いて窒化シリコン膜3及び酸化シリコン膜2を
選択的にエツチングして開孔部4を形成し、分離領域に
対応する領域のシリコン基板1の主表面を選択的に露出
させる。First, as shown in FIG. 1(a), a silicon oxide film 2 is grown to a thickness of 10 to 1100 nm on the main surface of a silicon substrate 1, and a silicon nitride film 3 is grown on the silicon oxide film 2.
is deposited to a thickness of 10 to 300 nm, and the silicon nitride film 3 and the silicon oxide film 2 are selectively etched using photolithography technology to form openings 4, and the silicon substrate in the region corresponding to the isolation region is etched. The main surface of 1 is selectively exposed.
次に、第1図(b)に示すように、開孔部4により露出
されたシリコン基板1の主表面を窒化シリコン膜3及び
酸化シリコン膜2をマスクとして等方性蝕刻法により除
去し、満5を形成する。Next, as shown in FIG. 1(b), the main surface of the silicon substrate 1 exposed through the opening 4 is removed by isotropic etching using the silicon nitride film 3 and the silicon oxide film 2 as masks. Form 5.
次に、第1図(c)に示ずように、溝5の表面を酸化し
、酸化シリコンM6を10〜300nmの厚さに成長さ
せ、その上に窒化シリコン膜7を10〜300 nmの
厚さに堆積する。このとき、窒化シリコン膜7は、満5
の上面及び側面の酸化シリコン膜6上に堆積され、また
溝5の上方に突き出た「ひさし」の周囲にも堆積される
。Next, as shown in FIG. 1(c), the surface of the groove 5 is oxidized to grow silicon oxide M6 to a thickness of 10 to 300 nm, and a silicon nitride film 7 is grown thereon to a thickness of 10 to 300 nm. Deposits in thickness. At this time, the silicon nitride film 7 fills up to 50%
It is deposited on the silicon oxide film 6 on the top and side surfaces, and also around the "eaves" projecting above the groove 5.
次に、第1図(d)に示すように、満5の上面に突き出
た[ひさしJをマスクとして、満5の底面に堆積された
窒化シリコン膜7及び酸化シリコン膜8を異方性蝕刻法
により除去し、開孔部8を形成する。従って、溝5の側
面には窒化シリコン膜7が残った状態となる。Next, as shown in FIG. 1(d), the silicon nitride film 7 and the silicon oxide film 8 deposited on the bottom surface of the wafer 5 are anisotropically etched using the eaves J protruding from the top surface of the wafer 5 as a mask. The aperture 8 is formed by removing the aperture 8 by a method. Therefore, the silicon nitride film 7 remains on the side surfaces of the groove 5.
次に、第1図(e)に示すように、開孔部8に露出され
たシリコン基板1を窒化シリコン膜7及び酸化シリコン
膜8をマスクとして異方性蝕刻法により除去し、溝9を
形成する。Next, as shown in FIG. 1(e), the silicon substrate 1 exposed in the opening 8 is removed by anisotropic etching using the silicon nitride film 7 and the silicon oxide film 8 as a mask to form the groove 9. Form.
次に、第1図(f)に示すように、窒化シリコン膜3及
び7をマスクとして、酸化処理を施して素子間分離酸化
膜10を形成する。Next, as shown in FIG. 1(f), an oxidation process is performed using the silicon nitride films 3 and 7 as masks to form an element isolation oxide film 10.
従来技術で素子間分離酸化膜を形成しなとき、酸化処理
による素子間分離領域の構法がりlは、その形成する素
子間分離酸化膜の厚さに比例して大きくなる。これに対
して本発明では、酸化処理による素子間分離領域の構法
がりをLとするとLは、等方性蝕刻法により開孔した開
孔部の深さによってのみ決定される。従って、従来技術
と本発明とで同じ厚さの素子間分離領域を形成する場合
、本発明での等方性蝕刻量と異方性蝕刻量の比を1;x
とすると、従来技術に比べ、本発明の素子間分離領域の
構法がりLは少なくなり、L=e−kx (kは定数)
となる。従って、本発明によると、従来技術の構法がり
に対してk xたけ小さくなり、分離領域の低減となる
。When an element isolation oxide film is not formed using the conventional technique, the construction thickness l of the element isolation region by oxidation treatment increases in proportion to the thickness of the element isolation oxide film formed. On the other hand, in the present invention, where L is the construction method of the element isolation region by oxidation treatment, L is determined only by the depth of the hole formed by the isotropic etching method. Therefore, when forming an element isolation region with the same thickness in the prior art and the present invention, the ratio of the isotropic etching amount to the anisotropic etching amount in the present invention is 1; x
Then, compared to the conventional technology, the construction method L of the isolation region of the present invention is smaller, and L=e−kx (k is a constant).
becomes. Therefore, according to the present invention, the structure size is reduced by k x compared to the construction method of the prior art, and the separation area is reduced.
上記実施例では、等方性蝕刻法によりシリコン基板を除
去して溝5を形成したが、その代りに開孔部4を酸化し
、その酸化シリコン膜を等方性蝕刻法で除去することに
より溝5を形成することもできる。その後の工程は、上
記実施例と同じである。このようにしても前記実施例の
同様に、素子間分離領域の構法がりは小さくなり、分M
領域の低減となる。In the above embodiment, the groove 5 was formed by removing the silicon substrate by isotropic etching, but instead, the opening 4 was oxidized and the silicon oxide film was removed by isotropic etching. Grooves 5 can also be formed. The subsequent steps are the same as in the above embodiment. Even in this case, as in the above embodiment, the structure of the isolation region becomes small, and
This results in a reduction in area.
以上説明したように、本発明は、溝の形成工程において
、等方性蝕刻に加えて異方性蝕刻を行うことにより、清
の構法がりが等方性蝕刻時にのみ発生するため、素子間
分離酸化膜の構法がりが小さい半導体装置を得ることが
できるという効果がある。As explained above, in the present invention, by performing anisotropic etching in addition to isotropic etching in the groove forming process, the structural gap in the structure occurs only during isotropic etching, so that separation between elements is achieved. This has the effect that it is possible to obtain a semiconductor device in which the structure of the oxide film is small.
第1図(a)〜(f)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図(a
)〜(e)は従来の半導体装置の素子分離方法の一例を
説明するための工程順に示した半導体チップの断面図で
ある。
■・・・シリコン基板、2・・・酸化シリコン膜、3・
・・窒化シリコン膜、4・・・開孔部、5・・・溝、6
・・・酸化シリコン膜、7・・・窒化シリコン膜、8・
・・開孔部、9・・・溝、10・・・素子間分離酸化膜
。1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for separating elements of a semiconductor device. ■...Silicon substrate, 2...Silicon oxide film, 3.
...Silicon nitride film, 4...Opening part, 5...Groove, 6
... silicon oxide film, 7... silicon nitride film, 8.
. . . Opening portion, 9 . . . Groove, 10 . . . Inter-element isolation oxide film.
Claims (1)
開孔部を有する第1の耐酸化性膜を形成する工程と、前
記第1の耐酸化性膜をマスクにして前記半導体基板を等
方性エッチングして前記開孔部より広い第1の溝を形成
する工程と、前記第1の溝の表面を覆う第2の耐酸化性
膜を形成する工程と、前記第1の溝の底面上の前記第2
の耐酸化性膜に前記第1の開孔部に対応する第2の開孔
部を形成して前記半導体基板の表面を露出させる工程と
、前記第1及び第2の耐酸化性膜をマスクとして前記第
1の溝の底面を異方性エッチングして第2の溝を形成す
る工程と、前記第1及び第2の耐酸性膜をマスクとして
酸化を行う工程とを含むことを特徴とする半導体装置の
製造方法。a step of forming a first oxidation-resistant film having a first opening in an element isolation region to be formed on a semiconductor substrate; forming a second oxidation-resistant film covering the surface of the first groove; and forming a second oxidation-resistant film on the bottom surface of the first groove. Said second
forming a second opening corresponding to the first opening in the oxidation-resistant film to expose the surface of the semiconductor substrate; and masking the first and second oxidation-resistant films. the step of anisotropically etching the bottom surface of the first groove to form a second groove; and the step of performing oxidation using the first and second acid-resistant films as masks. A method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7227888A JPH01244636A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7227888A JPH01244636A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01244636A true JPH01244636A (en) | 1989-09-29 |
Family
ID=13484661
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7227888A Pending JPH01244636A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01244636A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
KR100258857B1 (en) * | 1997-03-26 | 2000-06-15 | 김영환 | Manufacturing method for isolation structure of semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01206645A (en) * | 1988-02-15 | 1989-08-18 | Sharp Corp | Manufacture of semiconductor device |
-
1988
- 1988-03-25 JP JP7227888A patent/JPH01244636A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01206645A (en) * | 1988-02-15 | 1989-08-18 | Sharp Corp | Manufacture of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5182227A (en) * | 1986-04-25 | 1993-01-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
KR100258857B1 (en) * | 1997-03-26 | 2000-06-15 | 김영환 | Manufacturing method for isolation structure of semiconductor device |
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