JPS60135995A - Color code conversion memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an improvement of a color code conversion memory in a color display device such as a CRT.

[Background Technology] A color code conversion memory included in a color display device is also called a color lookup table, and has become popular in recent years as computer graphics has spread.

With the advancement of computer graphics,
The number of horn bits for color code conversion and the number of simultaneously displayed colors are increasing.

FIG. 1 is a block diagram showing a conventional general display device. In the figure, data to be displayed and address information are supplied from a CPU (central processing unit) 10 to a display control device 2O via a data bus and an address bus. The video memory 21 stores data displayed on the display screen of the display device, and is a memory for refreshing display patterns. Then, CRT controller 1-roller 2
2 is a dedicated LS that displays and controls the Rusk Scan type CR King.
This is an I controller that repeatedly outputs horizontal and vertical synchronizing signals and display addresses of the video memory 21 in accordance with the scanning of the display screen, and reads display data.

The parallel-to-serial converter 22 converts parallel data (display data) read from the video memory 21 into serial data (
(logical color code). The palette memory 23 is a color code conversion memory, and the D/A converter 24 converts the display color code into a linear signal for each of the three primary colors of RGB.

If you are using J3 in the above conventional example and want to change the color of the display screen, you only need to change the memory contents of the memory 23 of Valen 1, and there is no need to rewrite the video memory 21, so the display color can be changed. Can be changed quickly.

FIG. 2 shows a conventional pallet memory 23 which is attached to FIG. 1.
FIG. This palette memory 23 can only perform either write addressing or read addressing at the same time.

That is, the selector 23a selects a write address or a logical color code. Here, if a logical color code is selected, data in the RAM 23b corresponding to the color code is output as a display color code and appears on the display screen. Conversely, when the internal write address is selected, the write data is stored in the RAM 23b.
written to. However, when a write address is suddenly selected while the screen is being displayed, the color of the address specified by the write address appears. Therefore, the written data is output as a display color code. If the timing is not the blanking timing during the retrace period (although it is a very short time of λ0),
It appears as noise on the C display screen.

In J3 in the above conventional example, since the addressing in the palette memory is old and common, the screen is displayed (if the palette memory is used to display the background color, this time is also displayed). 11a (included in Ifil), when the color conversion data is updated, noise appears on the screen. Therefore, generally, color conversion data cannot be updated during the screen display period.

[Problems with the Background Art] In order to update the color conversion data without generating the above-mentioned noise, it is possible to control the color conversion update data to be automatically loaded only during retrace, but this control is complicated. There is a problem. Further, if the color conversion update data is inputted only during the blanking time during retrace, there is a problem that the 11 questions required for this purpose are extremely long. This wrap-around time typically requires as much as 64 u seconds for one access.

[Object of the Invention] The present invention has been made by focusing on the above-mentioned conventional problems, and by making color conversion mail always writeable, it is possible to write the color conversion mail at any time when rough 1 to wear is requested. The object of the present invention is to provide a color code conversion memory that can quickly update color conversion data.

[Summary of the Invention] The present invention provides, in addition to a circuit that sequentially provides a write address, data, and timing to a memory array, a plurality of bins from the memory array in response to an I:1 logical color code. The circuit that reads out 1~ at the same time is independently
It was set up.

Embodiment 1 of the Invention FIG. 3 is a block diagram showing an embodiment of the present invention, and is a block diagram of a palette memory.

First, as a main circuit on the writing side of color conversion data, there is a memory array composed of write decoders 40 to 4n, AND circuits 50 to 5n, and registers 60 to 6n. n
is the desired number, which is an integer multiple of the power of 2 of the number of bits of the logical color code (here the number of color passes, i.e. 3), which is 48 in this example, i.e. 2
When you multiply the fourth power by 318, you get 48.

Each of the AND circuits 50 to 5n receives a signal from the corresponding decoder 40 to 4n, and ANDs the signal with the write timing signal via an inverter. When receiving a lobe signal, data from the write data bus is stored.

Depending on the write address, among registers 60 to 6n,
A desired register, for example register 61, is designated. Furthermore, the write address determines which color to write. That is, in FIG. 3, among the registers 60 to 6n, the registers are R and G in order from the top.

It is connected to the B color buses 90R, 90G, and 90B, and the register 61 is 0. Here, [ is red, G is green, and B is blue. Then, at the same time, write timing conversion 8 and write data are sent.

The content of this light data is information indicating the depth or p degree of each color. In this way, color conversion data is incorporated.

To update the color conversion data, the same operations as those for writing the color conversion data described above can be repeated.1. By updating this color conversion data, various colors can be freely produced.

On the other hand, the circuits on the color code reading side include tri-state buffers 70 to 7n, a decoder 80 for logical color codes, R, G, and B color buses 90R,
There are 90G and 90B.

Each of the buffers 70-7[1 receives a signal indicating the depth of color from one of the corresponding registers 60-6n1),
When the output enable signal is received from the decoder 80, the display color code is changed to each power 5-buff, 9O
To R, 90G, 908: Output. Also, buffer 7O
~7n is tristate. A selection circuit can be constructed by combining this buffer and the color path. The above write circuit and read selection circuit are connected to other AND10
It is also possible to use a circuit 414 such as an R/select gate.

FIG. 4 is a timing chart of the embodiment shown in FIG. 3, and shows that reading and writing are operated at independent timing.

FIG. 5 is a circuit diagram of an example of an address port/counter used to continuously write data into the color code conversion memory at high speed.

In the figure, a CPU 1 and a palette memory 3O are connected by a boat decoder 101 and an address counter 102. First, the start address is loaded into the address counter 102 by NoJ error barre 1-load (boat 2), and the write timing (1 to boat 1)
Circle the color code. At the same time, the address counter is incremented by one. After that, if you only write the color code one after another, it will be OK.

FIG. 6 is a timing diagram of the address boat/counter shown in FIG. By writing in this way, by setting the start address only once, the subsequent color code data can be written continuously and at high speed in lengths 1-7.
``I can do just one job.

In the above embodiment, the color conversion code writing circuit is provided independently from the reading circuit, so that the color conversion registers 60 to 6n can be written to at any time.
Since the color conversion data can be continuously updated whenever the software requests, the operation is performed quickly. Of course, when updating the color conversion code, no noise will appear on the display screen.

In addition, by expanding the number of bits of the display color code compared to the number of bits of the logical color code, and defining the color density or brightness for each bit of the display color code, it is possible to express a very large number of colors. I can do it. For example, if the display color code is set to 9 pits, it has the expressive power of 512 colors. However, the colors that can be output simultaneously are determined by the number of bits of the logical color code. For example, in the case of 4 bits, up to 16 colors can be displayed simultaneously.

Although the color palette 30 and addresses/pointers 101 and 102 shown in FIG. 3 are an embodiment of the present invention, they can be replaced with the color palettes i to 23 of the display control device shown in FIG. In this case, a D/A converter 24 is used that is designed to change the amplitude of the output signal.

[Effects of the Invention] As described above, the present invention allows the color conversion memory to be written to at any time.
This has the advantage that the color conversion data can be updated at any time and the operation is quick.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional display system 6II device, FIG. 2 is a block diagram showing the palette memory in FIG. 1, and FIG. 3 is a block diagram showing the palette memory according to an embodiment of the present invention. 4 is a timing chart of the above embodiment, FIG. 5 is a circuit diagram showing an example of the address pointer/counter, and FIG. 6 is a timing diagram of the address pointer/counter. 20...Display control device, 21...Video memory, 2
3.30...Pallet memory, 40~4n...Writing decoder, 50~5"1...AND circuit, 60~
6n...Register, 70-7n...Tri-state buffer, 80...Logical color code decoder, 90R...R color bus, 90C+...G color bus, 90B...B color path, 101...I10
Port decoder, 102 . . . address pointer/counter. 0

Claims (1)

[Claims] (In a color code conversion memory used in color graphics, a plurality of storage means for storing converted color codes; data to be stored in this storage means, a write address of this data, and writing means for determining the writing timing; and selection means for selecting the storage contents of the storage means according to the M location for reading; the selection means is provided independently of the writing means, and the color conversion A color code conversion memory characterized in that the code can be updated at any time. (2. Claim 1 In JJI, the selection means simultaneously selects the contents of the plurality of storage means. A color code conversion memory characterized in that: (3) In claim 1, the means for providing the store address is an address pointer/counter that holds/counts the value of the write address; The /counter can set the value of the write start address, and when the write timing ends, it goes up from 1 to 1 and automatically specifies the next write address, and data can be written an arbitrary number of times in succession. A color code conversion memory characterized in that it is possible to update color conversion codes at high speed.