JPS60101797A - Semiconductor storage circuit device - Google Patents

Abstract

PURPOSE:To hold the relation between a precharging voltage and the operation point of a sense amplifier stably and shorten the access time of a memory cell by controlling the precharging voltage by using the output of the sense amplifier. CONSTITUTION:When a PMOSFET19 operates with a clock phi, a current begins to flow through a PMOSFET13 to charge parasitic capacity 14, and when the voltage on a bit line 6 rises up to a specific level, the output 40 of an inverter 42 of an output buffer front stage falls toward a level L; when it reaches the specific level, the output 41 of an inverter 43 rises toward a level H and reaches the level H by slight voltage variation on the line 6. No current flow through the FET13 at this point of time and the voltage on the line 6 is held a little bit higher than the operation limit of buffers 42 and 43. Then, when the clock phi turns off and a word line 5 is driven, the capacity 14 is charged up to a little bit higher than the operation point of the buffers 42 and 43, and when the voltage on the line 6 falls slightly, the buffers 42 and 43 operate to obtain output data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory circuit device, and more particularly to a semiconductor memory circuit device suitable for a microprogram memory that requires high-speed operation.

[Background of the invention]

FIG. 1 is a block diagram showing the general configuration of a microprogram ROM used in a microprocessor as an example of memory.

Data is stored in the memory cell 1, and the one corresponding to the address in the word line 5 is driven through the input buffer 2, decoder 3, word driver 4. The transistor 7 connected to the bit line 6 that intersects operates and generates a signal on the bit line 6, but if there is no transistor 7, this signal cannot be obtained.
, 0. The signal on the bit line 6 is output through an output buffer 8. In this case, discharging is generally faster than charging, so in order to increase speed and reduce power consumption, the potential of the bit line 6 is charged in advance by a precharge circuit 9, and the transistor 7 is used to charge only the necessary parts. A method of pulling it out is used.

If this transistor is not present, the potential of the bit line is maintained, so data of 1 or 0 is obtained depending on the presence or absence of the transistor 7. The same applies to decoder 3,
It can be charged with another precharge circuit 10 to perform the same operation as the memory cell 1.

On the other hand, FIG. 2 is a time chart showing the operation of the circuit of FIG. 1. This circuit operates in synchronization with the clock φ, precharging the bit line 6 in the first half and precharging the decoder 3 in the second half. Input buffer 2 uses clock φ
At the rising edge of , the address is fetched and the decoder 3 is driven.

The output of the decoder 3 is taken in by the word driver 4 at the falling edge of four pulses φ, and is sent to the word line 5. That is, the transistor 7 is driven. This generates an output on the bit line 6,
It is output through the output para 778.

From the above circuit, precharge circuit 9. Memory cell 1.
FIG. 3A shows the specific configuration of the output buffer 8. The precharge circuit 9 is PMO, S)
CM that combines raster 11 and NMO3) transistor 12
It consists of an OS inverter, PMO8) transistor 13.

When clock φ is applied, PMO 8) transistor 13 charges parasitic capacitance 14 on bit line 6. Here, when the NMO8) transistor of the memory cell is driven by the word line 5, the parasitic valley -114 is discharged and becomes lower than the threshold voltage of the inverter 42 consisting of the PMO8) transistor 15 and the NMO8) transistor 16. , the output falls. On the other hand, if there is no NMo5 transistor 7, the parasitic capacitance 1
4 does not change, and the output also maintains the H (High) level.

By the way, the parasitic capacitance 14 is the sum of capacitances of a large number of transistors, wiring, etc. connected to the bit line 6, and generally ranges from 5 to 10 pF. On the other hand, the NMOS transistor 7 is of a small size in order to achieve high integration, and its resistance during operation is often on the order of several tens of ohms.

Therefore, the parasitic capacitance 14 is discharged with an extremely large time constant. This results in a disadvantage of longer access time. The access time is determined by the time when the threshold value of the output buffer formed by the inverter 42 is reached. That is, as is clear from the input/output (V+-Vt) transfer characteristic graph of the inverter 42 shown in FIG. ΔvI11 changes from ΔvI11, and the output voltage at that time VL I+ t
This is the time until the voltage reaches the logical threshold voltage (V, , /2). If this access time is long, the cycle time of the microcomputer must be lengthened.
This was a bottleneck in increasing the speed of microcomputer systems using O8LSI.

In order to solve this problem, there has been an attempt to increase the sensitivity and shorten the access time by placing a sense amplifier for detecting minute level changes in the bit line at the front stage of the output terminal. In this case, no effect can be obtained unless the precharge voltage is set slightly higher than the operating point of the sense amplifier to shorten the time required for the sense amplifier to operate. However, the precharge voltage and the operating point of the sense amplifier vary depending on the element.

It changes depending on fluctuations in ambient temperature, power supply voltage, etc. In the end, it was necessary to take these fluctuations into account and provide some margin, and there was a limit to the reduction in access time.

[Purpose of the Invention] The purpose of the present invention is to shorten the access time of a memory cell, and more specifically, to reduce the access time of a memory cell, and more specifically, to reduce the precharge voltage and sense amplifier regardless of variations in device variations, ambient temperature, power supply voltage, etc. An object of the present invention is to provide a semiconductor memory circuit device that can maintain a stable relationship between operating points.

[Summary of the invention]

In the present invention, the output of the sense amplifier is used to control the charge pressure, so that the relationship between the precharge voltage and the operating point of the sense amplifier is always kept constant. Also,
In a preferred embodiment, a bipolar C is used in the precharge circuit.
Another feature is that it uses a MOS composite circuit to obtain a highly stable precharge voltage.

[Embodiments of the invention]

FIG. 4 is a circuit diagram showing one embodiment of the present invention, and corresponds to FIG. 3 of the conventional example. In FIG. 4, an output buffer is constructed by adding a CMOS inverter 43 consisting of a PMOS transistor 17 and an NMOS transistor 1B. This output is gate-controlled by clock φ (PMO8)
It is added to the PMO 8) transistor 13 for precharging through the transistor 19. Next, the operation of this embodiment will be explained using the time chart shown in FIG. In the previous cycle, the selected point of the memory cell was
If there is a Ranjistaf and the data is 1, the parasitic capacitance is 14
is discharged and the voltage of the bit line 6 has decreased, so the output of the inverter 42 at the front stage of the output buffer goes to H level.
The output 41 of the inverter 43 at the subsequent stage is at L level. Therefore, when PMO8) transistor 19 is activated by clock φ, PMOS transistor 13
Current begins to flow through the parasitic capacitance 14. As a result, the voltage on the bit line 6 increases, and when it reaches a certain level, the output 40 of the inverter 42 before and after the output level goes low.
Move to the level side. When this reaches a certain level, the output 41 of the inverter 43 at the subsequent stage moves to the H level side. In this state, the relationship between the voltage of the bit line 6 and the output 41 of the inverter 43 at the rear stage of the output buffer is as follows:
Therefore, after the output 41 of the inverter 43 after the output buffer starts to move to the H level side, the voltage on the bit line 6 reaches the H level even if the voltage on the bit line 6 changes slightly. At this point, PMO8) transistor 13
current will no longer flow, and the voltage on bit line 6 will remain at a point just above the operating limit of output buffer 42,43. Next, when clock φ turns off, PMO
8) The transistor 19 is made non-conductive, and the voltage of the bit line 6 is read out through two stages of inverters (42, 43), resulting in a general ROM configuration. At this point, the word line 5 is driven, the NMOS transistor of the memory cell extracts the charge from the rose capacitor t14, and the voltage of the bit line 6 starts to drop to 9, but it slightly exceeds the operating point of the output buffers 42 and 43. It has been charged to the point where it was. Therefore, when the bit line voltage drops slightly, the output buffers 42, 43 are activated and data is available at the output. The voltage change at this time depends on the gain of the output buffer and the delay time during precharging, but generally about 0.1 to 0.4 V is sufficient, and the access time is extremely short. In addition, since the precharge voltage is controlled by the output parts 7a 42 and 43, which correspond to the sense amplifier, the relationship between the precharge voltage and the operating point of the sense amplifier is affected by variations in the ambient temperature, power supply voltage, etc. of the elements. Extremely stable operation is possible without being affected.

FIG. 6 shows the input/output transfer characteristics of the inverters 42 and 43 in FIG. 4. As is clear from this figure, the voltage V□1 after precharging the bit line 6 is set to the logical threshold voltage (V, , /2) of the inverter 42 in the previous stage.
If the setting is set at a slightly higher value, the output 41 of the inverter 43 at the subsequent stage will have a value sufficiently close to the t4i source voltage when the charge on the bit line 6 is not extracted by the NMOS transistor 7 (dotted line in FIG. 6). Indicates V p r 2. Also, N
When the charge of the bit line 6 is extracted by the MOS transistor 7 (actual a in Fig. 6), the output of the inverter 43 in the subsequent stage becomes a value sufficiently close to the ground voltage (OV) due to the extremely slight voltage fluctuation Δ■III. Indicates v4. As described above, the reason why the output voltage of the subsequent inverter 43 changes greatly due to a slight change in the input voltage of the preceding inverter 42 is due to the synergistic effect of the gains of the two inverters 42 and 43, as described above.

The output 41 of the inverter 43 in the latter stage supplies precharge charges via the PMOS transistor 19.
Since the OS transistor 13 is controlled, the voltage level V p r I of the bit line 6 after precharging is equal to that of the MOS
) The transistors 13, 15°, 16, 17, 18, 19 may be set at the optimum position.

FIG. 7 is a circuit diagram showing another embodiment of the present invention. The difference between this circuit and the circuit shown in FIG. 4 is that in FIG.
The point is that the part that was previously performed in the previous example is replaced with a precharge circuit 70 that includes a bipolar transistor. In this circuit 70, the PMO8) transistor 20 and the Bibo2 transistor 22 have the same precharge function as the PMO8) transistor 13 in FIG. Also, PMO8 in Figure 4)
In place of the transistor 19, a bipolar transistor 22
An NMOS transistor 21 is connected to the base of the bit line 6, the base current is bypassed in the latter half of the clock, the bipolar transistor 22 is made non-conductive, and the charge supply to the bit line 6 is cut off when the charge from the bit line 6 is extracted.

Bybo 2 used in the precharge circuit of this example
Since the transistor is essentially a current-driven element and can handle a relatively large current, precharging can be performed more stably and at high speed.

The embodiment of FIG. 7 is particularly effective when bit line selection is added as shown in FIG. In the circuit of FIG. 8, for multiple bit lines, output voltage (NM) is applied to each bit line (JS transistors 230 to 23
3 is added, and according to the selection signal 5o=Ss, the voltage of one bit line is applied to the inverter 42 at the front stage of the output voltage 7a. On the other hand, in the precharge circuit 80, the bipolar transistor 22 shown in FIG.
This is a change. By the way, since the selection signals SO to S3 are given at the timing of the input buffer output in FIG. may change. However, in the circuit 80 of FIG. 8, since the base of the bipolar transistor 820 is common, the voltage of each bit line is almost the same, and the selection signal 5o-
The switching of 8s has almost no effect on the precharge operation.

The function similar to the circuit in Figure 8 is PMOS for precharging.
This can also be achieved by inserting diodes 240-243 between the transistor 13 or bipolar transistor 82 and the bit lines 60-63. That is, in the circuit of FIG.
Diodes 240-243 and PMO8) Transistor 13
Alternatively, since the connection point of bipolar transistor 82 is common, the voltages of bits a60 to a63 are almost the same during precharging.

Similarly, for memory cell 1, the gate is a word and a gland.

Although the explanation has been given by taking as an example a device configured by the presence or absence of a MOS transistor whose source or drain is connected to a bit line, the present invention is not limited to this, and includes a bipolar transistor, a plurality of MOS transistors, a bipolar transistor, and a bipolar transistor. .

Alternatively, the present invention can also be applied to a memory cell composed of a flip-flop or the like formed by a mixture of these.

〔Effect of the invention〕

According to the present invention, the relationship between the precharge voltage of the memory and the operating point of the sense amplifier is determined by variations in the elements.

Stable control is possible regardless of fluctuations in ambient temperature, power supply voltage, etc. Therefore, the difference between the two can be set to the minimum necessary value,
A semiconductor memory circuit device that detects bit line voltage changes at high speed can be obtained. Furthermore, since the sense amplifier and the output buffer are also used, the configuration of one circuit becomes simple.

Furthermore, according to the present invention, by using a bipolar transistor f:f in the circuit that precharges the bit line, it is possible to quickly precharge the large parasitic capacitance load of the bit line that accompanies the increase in memory capacity. There is also.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the general configuration of the ROM, FIG. 2 is a time chart explaining the operation of the ROM, FIG. 3A is a circuit diagram showing the specific configuration of the precharge circuit and output buffer, and FIG. B is a diagram showing its input/output transfer characteristics, FIG. 4 is a circuit diagram showing an example of the present invention, FIG. 5 is a time chart explaining the operation of the circuit shown in FIG. 4, and FIG. 6 is an output buffer. 7 to 9 are circuit diagrams showing other embodiments of the present invention. 1...Memory cell, 2...Input cover 7a, 3...
Tecoder, 4... Word driver, 5... Word line, 6... Bit line, 7... Transistor, 8...
Output buffer, 9.10.13... Precharge circuit, 14... Parasitic capacitance, 22... Bipolar transistor, 42°43... Inverter, 70. dθ...
Precharge circuit, 82...Marche Minta transistor. Agent Patent Attorney Tatsuyuki Unuma 1 dent 70 Output 2 Kokuto 3m (A) 'Vt7LV''- Invitation 40 50th q Senko Tosuke 80 J1. CC to T line

Claims (1)

[Claims] 1. Memory cells arranged in a matrix between bit lines and word lines to store data; a precharge circuit that charges the bit lines prior to data access; In a semiconductor integrated circuit device equipped with a data readout output buffer for storing stored data, a precharge circuit charges a bit line.
control the pressure as well as the output of the output buffer for data reading;
A semiconductor integrated circuit device characterized in that the precharge voltage is set near a minimum value necessary for the output buffer to operate. 2. A semiconductor integrated circuit device according to claim 1, characterized in that the memory cell is configured with or without a MOS transistor whose gate is connected to a word line and whose source or drain is connected to a bit line. 3. Claim 1 is characterized in that the precharge circuit for charging a plurality of bit lines is a multi-emitter bipolar transistor having multi-emitters corresponding to the respective bit lines and having a common base. Semiconductor memory circuit device.