JPS6476352A - Data transfer device - Google Patents
Data transfer deviceInfo
- Publication number
- JPS6476352A JPS6476352A JP23553087A JP23553087A JPS6476352A JP S6476352 A JPS6476352 A JP S6476352A JP 23553087 A JP23553087 A JP 23553087A JP 23553087 A JP23553087 A JP 23553087A JP S6476352 A JPS6476352 A JP S6476352A
- Authority
- JP
- Japan
- Prior art keywords
- transfer
- interface
- performs
- data
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To realize the connection to an external device having an interface incompatible with existing channel devices by using an interface which performs the transfer of data, a means which performs the transfer of control signals, and a means which performs the transfer of data to and from a memory. CONSTITUTION:A channel device interface part 3 is connected to a channel device of the existing information processor at the side of an input/output device and performs the transfer of a start signal and the signal of a control system for interruption request, etc. A memory interface part 2 is connected to a memory access system of the existing information processor and performs the direct transfer of data to and from the memory. An external device interface part 4 is connected to an external device 6 and controls the transfer of data to and from the device 6. These interface parts 2-6 are controlled by a common control part 5. In such constitution, the connection is secured to the device 6 of high transfer speed which contains an interface different from an input/ output interface of the information processor. Thus the transfer of data is controlled between the main memory of the existing information processor and the device 6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23553087A JPS6476352A (en) | 1987-09-18 | 1987-09-18 | Data transfer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23553087A JPS6476352A (en) | 1987-09-18 | 1987-09-18 | Data transfer device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6476352A true JPS6476352A (en) | 1989-03-22 |
Family
ID=16987339
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23553087A Pending JPS6476352A (en) | 1987-09-18 | 1987-09-18 | Data transfer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6476352A (en) |
-
1987
- 1987-09-18 JP JP23553087A patent/JPS6476352A/en active Pending
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