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JPS5654509A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS5654509A
JPS5654509A JP12940579A JP12940579A JPS5654509A JP S5654509 A JPS5654509 A JP S5654509A JP 12940579 A JP12940579 A JP 12940579A JP 12940579 A JP12940579 A JP 12940579A JP S5654509 A JPS5654509 A JP S5654509A
Authority
JP
Japan
Prior art keywords
data
bus
area
cpu1
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12940579A
Other languages
Japanese (ja)
Inventor
Iwao Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12940579A priority Critical patent/JPS5654509A/en
Publication of JPS5654509A publication Critical patent/JPS5654509A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To facilitate data transfer and to improve the processing efficiency of CPU by doubling memory areas in a memory and by using one area for data transmission and reception when the other is used for arithmetic.
CONSTITUTION: Input-output control parts 41W4n input data from a controlled system to data memory area II via system bus B2 in advance. To read the data of the controlled system by CPU1, data area II is only connected to unit bus B1. With a switching signal from CPU1, bus control part 6 generates selective signals S1 and S2 to put selectors 81, 82, 91, and 92 into operation. Consequently, data area II is connected to data bus B1 and address bus A1 and CPU1 performs processing by communicating with data area II. During this period, data area I fetches data from input-output control parts via data bus D2 and address bus A2 for the next processing.
COPYRIGHT: (C)1981,JPO&Japio
JP12940579A 1979-10-09 1979-10-09 Sequence controller Pending JPS5654509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12940579A JPS5654509A (en) 1979-10-09 1979-10-09 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12940579A JPS5654509A (en) 1979-10-09 1979-10-09 Sequence controller

Publications (1)

Publication Number Publication Date
JPS5654509A true JPS5654509A (en) 1981-05-14

Family

ID=15008733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12940579A Pending JPS5654509A (en) 1979-10-09 1979-10-09 Sequence controller

Country Status (1)

Country Link
JP (1) JPS5654509A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60100207A (en) * 1983-11-02 1985-06-04 Mitsubishi Electric Corp Plant control system
JPS60108902A (en) * 1983-11-18 1985-06-14 Oki Electric Ind Co Ltd Process input/output method
WO1989011685A1 (en) * 1988-05-18 1989-11-30 Fanuc Ltd System for detecting state transition of a pc

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60100207A (en) * 1983-11-02 1985-06-04 Mitsubishi Electric Corp Plant control system
JPS60108902A (en) * 1983-11-18 1985-06-14 Oki Electric Ind Co Ltd Process input/output method
WO1989011685A1 (en) * 1988-05-18 1989-11-30 Fanuc Ltd System for detecting state transition of a pc

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