JPS647528A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS647528A JPS647528A JP62161049A JP16104987A JPS647528A JP S647528 A JPS647528 A JP S647528A JP 62161049 A JP62161049 A JP 62161049A JP 16104987 A JP16104987 A JP 16104987A JP S647528 A JPS647528 A JP S647528A
- Authority
- JP
- Japan
- Prior art keywords
- patterns
- lead
- conductive layers
- insulator
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Abstract
PURPOSE:To facilitate the manufacture by a method wherein insulator patterns are formed on conductive layers on a substrate; multiple lead patterns are formed on the conductive layers exposed from the insulator patterns, and the insulator patterns and the lead patterns are peeled off from the conductive layers to form a lead carrier. CONSTITUTION:Insulator patterns 14 with lead pattern type openings are formed on conductive layers 12, 13 on a substrate 11 while lead patterns 15 are formed on the conductive layers 12, 13 exposed from the insulator patterns 14 by electroplating process using the conductive layers 12, 13 as common electrodes. Later, these insulator patterns 14 and the lead patterns 15 are peeled off from the conductive layers 12, 13 of the substrate 11. Thus, a lead carrier with the lead patterns 15 in narrow width and pitch can be easily manufactured. Furthermore, the manufactured lead carrier 16 is integrated comprising the insulator patterns 14 and the lead patterns 15 located on the same plane so that the lead patterns 15 may be prevented from bending and breaking due to deadweight or handling.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62161049A JPS647528A (en) | 1987-06-30 | 1987-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62161049A JPS647528A (en) | 1987-06-30 | 1987-06-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS647528A true JPS647528A (en) | 1989-01-11 |
Family
ID=15727633
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62161049A Pending JPS647528A (en) | 1987-06-30 | 1987-06-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS647528A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03220740A (en) * | 1990-01-25 | 1991-09-27 | Nec Corp | Structure of semiconductor device |
-
1987
- 1987-06-30 JP JP62161049A patent/JPS647528A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03220740A (en) * | 1990-01-25 | 1991-09-27 | Nec Corp | Structure of semiconductor device |
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