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JPS57173940A - Mask for photoetching - Google Patents

Mask for photoetching

Info

Publication number
JPS57173940A
JPS57173940A JP5899581A JP5899581A JPS57173940A JP S57173940 A JPS57173940 A JP S57173940A JP 5899581 A JP5899581 A JP 5899581A JP 5899581 A JP5899581 A JP 5899581A JP S57173940 A JPS57173940 A JP S57173940A
Authority
JP
Japan
Prior art keywords
mask
split
chip
pattern
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5899581A
Other languages
Japanese (ja)
Inventor
Arimasa Abe
Mitsutaka Kato
Katsuhiro Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP5899581A priority Critical patent/JPS57173940A/en
Publication of JPS57173940A publication Critical patent/JPS57173940A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23QDETAILS, COMPONENTS, OR ACCESSORIES FOR MACHINE TOOLS, e.g. ARRANGEMENTS FOR COPYING OR CONTROLLING; MACHINE TOOLS IN GENERAL CHARACTERISED BY THE CONSTRUCTION OF PARTICULAR DETAILS OR COMPONENTS; COMBINATIONS OR ASSOCIATIONS OF METAL-WORKING MACHINES, NOT DIRECTED TO A PARTICULAR RESULT
    • B23Q7/00Arrangements for handling work specially combined with or arranged in, or specially adapted for use in connection with, machine tools, e.g. for conveying, loading, positioning, discharging, sorting
    • B23Q7/16Loading work on to conveyors; Arranging work on conveyors, e.g. varying spacing between individual workpieces

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

PURPOSE:To exclude inferior chips split off the end part, and to manufacture only chips being hard to generate split of wafer by a method wherein constitution of pattern is made as to have only the arrangement of pattern units corresponding to chip units having no split of end part on the wafer. CONSTITUTION:When an example of constitution of a mask 1 for photoetching wherein the diameter of an Si wafer 4 is 50phimm., and the size of a chip is 3X3mm./ ? is shown, constitution 2a of pattern of the mask 1a is consisting of the arrangement of 32 pattern units corresponding to chip units of the total number 164 having no split of end part. Because the photoetching mask thereof is consisting of only the pattern units corresponding to the chip units having no split of end part on the wafer like this, when the mask thereof is applied as a mask for electrode wiring, for example, to mistake an inferior chip being split a part thereof for an excellent article is not occurred when inspection of electric characteristic is to be performed, and the inferior chip can be checked precisely. Moreover when the mask thereof is applied as a mask for formation of the back etching pattern, production of split of wafer can be suppressed.
JP5899581A 1981-04-17 1981-04-17 Mask for photoetching Pending JPS57173940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5899581A JPS57173940A (en) 1981-04-17 1981-04-17 Mask for photoetching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5899581A JPS57173940A (en) 1981-04-17 1981-04-17 Mask for photoetching

Publications (1)

Publication Number Publication Date
JPS57173940A true JPS57173940A (en) 1982-10-26

Family

ID=13100425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5899581A Pending JPS57173940A (en) 1981-04-17 1981-04-17 Mask for photoetching

Country Status (1)

Country Link
JP (1) JPS57173940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263227A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263227A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Manufacture of semiconductor device

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