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JPS6462736A - Error detecting circuit - Google Patents

Error detecting circuit

Info

Publication number
JPS6462736A
JPS6462736A JP62220620A JP22062087A JPS6462736A JP S6462736 A JPS6462736 A JP S6462736A JP 62220620 A JP62220620 A JP 62220620A JP 22062087 A JP22062087 A JP 22062087A JP S6462736 A JPS6462736 A JP S6462736A
Authority
JP
Japan
Prior art keywords
parity
error
signal
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62220620A
Other languages
Japanese (ja)
Inventor
Kentaro Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62220620A priority Critical patent/JPS6462736A/en
Publication of JPS6462736A publication Critical patent/JPS6462736A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To detect a place where an error is generated, and to easily execute an error processing and a problem analysis in a short time, by checking the legality of a data in both at the time of write and at the time of read-out to and from a storing circuit. CONSTITUTION:A parity generating circuit 1 inputs a data 11 from an input data 10 and outputs a parity generating signal 13, and an exclusive OR circuit 2 outputs an input data error signal 21, when a discrepancy of a parity signal 12 in the input data 10, and the parity generating signal 13 is detected. An output data checking circuit 4 executes a parity check by parity checking circuits 41, 42 by each of a data 31 in an output data which has been read out of a storing circuit 3, a parity signal 32 and a parity generating signal 33, and outputs an output data error signal 44 from an AN circuit 43, when both the parity checks have shown an error, respectively. In such a way, since a place where an error has been generated can be detected, an error processing is facilitated.
JP62220620A 1987-09-02 1987-09-02 Error detecting circuit Pending JPS6462736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62220620A JPS6462736A (en) 1987-09-02 1987-09-02 Error detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62220620A JPS6462736A (en) 1987-09-02 1987-09-02 Error detecting circuit

Publications (1)

Publication Number Publication Date
JPS6462736A true JPS6462736A (en) 1989-03-09

Family

ID=16753825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62220620A Pending JPS6462736A (en) 1987-09-02 1987-09-02 Error detecting circuit

Country Status (1)

Country Link
JP (1) JPS6462736A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04153838A (en) * 1990-10-18 1992-05-27 Fujitsu Ltd Error check circuit for dual system
JPH05108386A (en) * 1991-10-17 1993-04-30 Nec Corp Information processor
US5797275A (en) * 1993-12-22 1998-08-25 Telefonaktiebolaget Lm Ericsson Air-cooling system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04153838A (en) * 1990-10-18 1992-05-27 Fujitsu Ltd Error check circuit for dual system
JPH05108386A (en) * 1991-10-17 1993-04-30 Nec Corp Information processor
US5797275A (en) * 1993-12-22 1998-08-25 Telefonaktiebolaget Lm Ericsson Air-cooling system

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