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JPS5333062A - Packaging method of semiconductor integrated circuit - Google Patents

Packaging method of semiconductor integrated circuit

Info

Publication number
JPS5333062A
JPS5333062A JP10743876A JP10743876A JPS5333062A JP S5333062 A JPS5333062 A JP S5333062A JP 10743876 A JP10743876 A JP 10743876A JP 10743876 A JP10743876 A JP 10743876A JP S5333062 A JPS5333062 A JP S5333062A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
packaging method
lead wires
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10743876A
Other languages
Japanese (ja)
Inventor
Toshiaki Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP10743876A priority Critical patent/JPS5333062A/en
Publication of JPS5333062A publication Critical patent/JPS5333062A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To easily connect an IC and lead wires by coating a positive type photoresist containing a conductive substance on the entire surface of the IC, aligning the lead wires provided to a flexible insulation tape to the bonding pads on the IC, removing the unnecessary portions of the resist thereafter hardening the resist.
COPYRIGHT: (C)1978,JPO&Japio
JP10743876A 1976-09-08 1976-09-08 Packaging method of semiconductor integrated circuit Pending JPS5333062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10743876A JPS5333062A (en) 1976-09-08 1976-09-08 Packaging method of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10743876A JPS5333062A (en) 1976-09-08 1976-09-08 Packaging method of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5333062A true JPS5333062A (en) 1978-03-28

Family

ID=14459141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10743876A Pending JPS5333062A (en) 1976-09-08 1976-09-08 Packaging method of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5333062A (en)

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