JPS5990290A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a current to an unselected array and to reduce power consumption by controlling source potentials of transistors (TR) forming flip-flops of a memory cell according to whether they are selected or not. CONSTITUTION:For example, a word line WL1 is held at a high level and the control line CL to which common sources of intersection-connected TRs Q42 and Q52 forming an FF of memory cells MC1, MC2... of the array are connected in common is lowered from a high potential to a low potential, selecting the memory cell MC1. In this case, lines CL of unselected arrays are at the high potential, so even when the line WL1 is held at the high potential, almost no current flows to the unselected arrays to reduce the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory array in which memory cells each having a transistor (MOS) transistor drain-gate coupled flip-flop are arranged in an array; A semiconductor memory comprising a word line connecting memory cells and a bit line connecting memory cells in a column direction of the memory array, and selecting a memory cell in a row direction of the memory array by activating the word line. Regarding equipment.

[Technical background of the invention and its problems]

A conventional semiconductor memory device is shown in FIG. MOS transistor Q41. Qs+iI:I is connected to the drain and gate to form a flip-flop circuit, and the load resistor &.

&l and transmission MO8) transistor Qar + Qs
s constitutes one memory cell MC. A large number of such memory cells are arranged in an array to form a memory array. The memory cells in the row direction of this memory array are connected to the word line WL, and the memory cells in the column direction are connected to the pin lines BL and B[. Load transistors Qu + Q2 are installed at the ends of the bit lines BL and 3L.
1 is connected. In a semiconductor memory device configured in this way, the voltage of one of the M word lines? : A row is selected by setting it to the negative level, and a desired memory cell is accessed by selecting one pair of N bit lines and reading its signal.

However, in accessing such a conventional semiconductor memory device, when one word line is selected and the voltage is raised to a high level, current flows through the bit lines of all columns. In order to access a memory cell, only the selected column needs to be activated, and the current flowing to the bit lines of other columns is wasted (for example, 64).
When memory cells are configured as an array with the same number of rows and columns in AM, there are 256 columns. Since approximately 200 μ·A flows per row, the total current reaches approximately 51 mA. This wasteful current flows, accounting for most of the power consumption of the entire semiconductor memory device, and has become a problem. [Object of the Invention] The present invention has been made in consideration of the above circumstances.

It is an object of the present invention to provide a semiconductor memory device with low power consumption in which current flowing through unselected columns is not wasted.

[Summary of the invention]

In order to achieve this object, the semiconductor memory device according to the present invention includes MOS transistors constituting seven lip-flops of memory cells.
The source terminals of the transistors are commonly connected in a predetermined number of Ω columns, and a control line is provided to control the voltage of these source terminals. It is characterized in that only two selected columns are activated by setting the potential of the power supply.

[Embodiments of the invention]

An embodiment of the present invention will be described using FIG. 2.

Each memory cell is a drain-gate coupled MOS try.
Sis! Flip-flop circuit consisting of J' Q4z + Q82, load resistors R11, R21 and 2 transmission M
O8) A flip-flop circuit consisting of transistors Q32 + Q62. The source terminals of the MOS transistors Q42 and Q minor connected together are connected to a common control line C for memory cells belonging to the same column.
Connect to L. A control line CL is provided for each column. That is, each column is provided with a pair of bit lines BL, BL and one control line CL.

Next, I will explain the operation. First, the voltage of the word line of the selected row is set to high level. At the same time, the potential Vs of the control line of the selected column is set to 0■. The potential VB of the control line of the other unselected columns remains at the predetermined potential VS'S. For example, when accessing the memory cell MCI in FIG. 2, the potential of the word line WLI is set to high level, and the potential Vs of the second control line CL is lowered to OV. The potential (2) of the control line CL when not selected is set such that the difference between the power supply voltage (2) and the power supply voltage (2) does not become smaller than the threshold value (7) of the MOS transistor. That is, Vs
(Vo.

- Must be 7 guns. When the memory cell MCI is accessed, the potential of the bit line BL or BL is lowered depending on the state of the flip-flop circuit of the memory cell MCI, and the sense amplifier (not shown) connected to the bit lines BL and BL lowers the potential of the bit line BL. sensed.

Since the potential Vs of the control line CL of the selected column is lowered to OV, current flows, but the control line C of the unselected column
Since the potential Vs of L is a higher potential, only a small amount of current flows through the unselected columns.

This means that even if the potential of the word line becomes high, the gate potential of MOS) transistor Q42 + Qsz and MOS) transistor Q32. as seen from the common source of the flip-flop circuit. The gate potentials of Q6 z both become low,
This is because the current drawn from the bit lines BL, BL becomes smaller. Also MOS) transistor Q42. Qs
z, the substrate bias of the transmission MOS transistors Qsg+Qgz increases, so the threshold voltage increases and the current decreases significantly. In fact, in the past, the current flowing through non-selected columns was more than 90% of the total current, so in the semiconductor memory device according to this embodiment, the total current during operation is 15 to 19% of the conventional one.
It can be reduced to about 1. Then, by distributing the obtained surplus current to peripheral circuits, etc., higher speed operation can be realized.

In this embodiment, when the column is not selected, the potential Vs'It of the control line CL is set to a predetermined potential VB N S, and if this column is to be selected, the potential Vs' of the control line CL needs to be lowered to 40V. In order to prevent the potential Vs of the control line CL from being suddenly lowered externally, the characteristics of the MOS transistors Q421Q52 that constitute the roller flip-flop circuit are not exactly the same, so if the potential Vs is suddenly lowered,
This is because there is a possibility that the stored contents may be reversed due to the difference in the discharge characteristics of the transistor Q42°QH (MOS).

Next, a second embodiment of the present invention will be explained using FIG. 3. The semiconductor memory device according to this embodiment has an n-bit configuration, such as a 4-bit configuration or an 8-bit configuration, in which n memory cells are simultaneously accessed. One memory cell is constituted by the MOS transistor Q431 Qas, the load resistor R23, and the transmission MOS transistors Q3a and Qas that constitute the flip-flop circuit. n memory cells MCl0°-, MC1n, and n
1liffi memory cell/L/MC20,-,MC
2n are arranged in mirror-image symmetry, and the sources of the MOS transistors constituting the flip-flop circuits of these 2n memory cells are commonly connected to one control line CL3. The potential of this control line CL3 is controlled by a MOS transistor Qos + QJ31 QxsK, and the potential of the control line φ8. φ8M runs in the column direction and is controlled by the column decoder output signal.

Next, the operation of this embodiment will be explained. The control line φ8 is fixed to the lower reference potential Vss or a voltage about 1 V higher than it, and the control line φsM is set to Vss when selected by the column decoder - and higher than the control line φ8M by a threshold voltage when not selected. It becomes an intermediate voltage.

First, consider the behavior when no column is selected. If neither word line WLl nor WLQ is selected, M
OS transistor Q13. Both Q23 are off.

The memory cell current flows through the MOS transistor 403, and the potential V83 of the control line CL3 is approximately 1 to 2V. In this state, the current flows through the resistance R13+ of each memory cell.
It only flows through R23. Word line WL 1, VJ
If either one of IJ 2 is selected -MO8
) Either one of the transistors Q+31Q23 is turned on, but the first control line φ5M is at an intermediate potential because no column is selected, and no current flows through the control line CL3. Therefore, the potential V, 3 of the control line CL3 is at an intermediate level, and the current drawing ability of each memory cell is weak, so a large current will not flow. In this way, when a column is not selected, a large current will not flow whether or not the word line is selected.Next, think about the operation when a column is selected.

When a column is selected, the potential of the control line φ8M is lowered to the reference potential vss by the column decoder output signal.

When one of the word lines wr, +, WL2 is selected, one of the MOS transistors QI31Q23 becomes conductive, and the potential 3 of the control line CLa also drops to the reference potential vss.

MO8) Transistor Q3 for transmission of selected memory cell
3°Qes and MOS transistor Q43. Q53's substrate IA decreases, and the threshold voltage decreases.At the same time, the potential difference between the gate leases increases, causing a large current to flow, and one side of the pair of bit lines quickly reaches a low potential. The contents of the memory cell are transmitted to the bit line.Also, if none of the word lines WL, , WL, are selected, the potential 83 of the control line CL3 is set to the reference potential "s".
At the same time, the low potential side of each memory cell also drops to the reference potential vss. Therefore, transmission MOS transistor Q3
B1Q63 is in the off state and no large current flows.

As described above, according to this embodiment, even in a multi-bit semiconductor memory device, the current can be significantly reduced in tC as in the first embodiment. Further, in many cases, it is preferable to route the control lines that are commonly connected to the sources in the row direction from the viewpoint of their characteristics and design.

Therefore, this embodiment can be applied not only to a semiconductor memory device having a multi-pit configuration but also to a 1-bit configuration.

Next, a third embodiment of the present invention will be described using Figure 4. The memory cells are configured similarly to the second embodiment, and a control line CL4 commonly connects the sources of each memory cell.
is running in the row direction. This control line CL4 is a control line φ controlled by the output signal of the column decoder. By M.O.
Controlled via S transistor Qo4°Q+4. The potential of this control line φ value is at a high level when the 2nd column is selected, and at a low level when the 1st valve is selected. Control line φ when selecting a column. When the potential of the control line φ becomes high level, the MOS transistor Q14 is turned on and a current flows.However, when the outer valve is selected, the control line φ. When the potential of MC8) falls to a low level, transistor Q14 turns off and almost no current flows.

In this way, according to this embodiment, MC8) transistor Qr
Since < is not connected to the word line WL+, the load on the word line becomes lighter and signal propagation delay can be prevented.

Note that in the previous embodiment, the semiconductor memory device of a memory cell that uses a resistor as a load was described, but the CMO
It goes without saying that the present invention can also be applied to semiconductor memory devices that use a P-channel MOS transistor as a load such as an S memory, or a semiconductor memory device that uses a depletion type MOS transistor as a load and has memory cells of an E/D type configuration. .

Furthermore, the present invention is not limited to the configuration in which the bit lines BL, BL are pulled up by the MOS transistor Qll+Q21 which is always in a conductive state as shown in FIG.
The present invention can also be applied to a semiconductor memory device in which the bit lines BL, BL are precharged by a clock.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to eliminate wasteful current flowing through selected columns and to reduce power consumption. By distributing the extra power due to this low power consumption to peripheral circuits,
The speed of the entire device can be increased.

Furthermore, in the present invention, the potential of the word line rises and the potential of the control line falls at the same time. Also, the potential of the word line falls and the potential of the control line rises simultaneously. Since they can be performed simultaneously, the selection and non-selection operations of columns and rows can be performed in a short time, and further speeding up can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional semiconductor memory device, FIG. 2 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention, and FIG. 3 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the present invention. Circuit Diagram 2 Showing Device FIG. 4 is a circuit diagram showing a semiconductor memory device according to a third embodiment of the present invention. WL 4 WL+, WL 2 ... word line, B
L, BL, BLo. BLo, BLn, BLn-bit line, CL, C
L3. CL4゜φ3. φ3M+φ. ...control line, R
11+ R21+ R1□, R221R131R33・
...Resistance, Q4+ + Qs1+ Q4r+ Qsz
+Q43 +Qsa...MOS transistor b Q
31, Qa+, Q32 +QL2+Qsa+
Q as-transmission MO3) transistor, MC. MCI, MC2, MCl0. MC1n, MC20, MC
2n--Memory cell.

Claims (1)

[Claims] A memory array in which memory cells having drain-gate coupled flip-flops (MOS) transistors are arranged in an array, and a word line connecting the memory cells in the row direction of the memory array. 2. A semiconductor memory device comprising a bit line connecting memory cells in a column direction of the memory array, and selecting memory cells in a row direction of the memory array by activating the word line. the MO constituting a flip-flop of the memory cell;
A control line is provided in which the source terminals of the S transistors are commonly connected in a predetermined number of columns and the potentials of these source terminals are controlled.