JPS5967018U - bias circuit - Google Patents
bias circuitInfo
- Publication number
- JPS5967018U JPS5967018U JP16023282U JP16023282U JPS5967018U JP S5967018 U JPS5967018 U JP S5967018U JP 16023282 U JP16023282 U JP 16023282U JP 16023282 U JP16023282 U JP 16023282U JP S5967018 U JPS5967018 U JP S5967018U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- bias circuit
- transistors
- bases
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
- Logic Circuits (AREA)
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のバイアス回路からなる差動増幅器の回路
図、第２図はこの考案のバイアス回路を適用した差動増
幅器の回路図、第３図はこの考案のバイアス回路を輝度
信号の復調回路に応用した時の回路図を示す。
図中、Ｑ１〜Ｑ８はトランジスタ、Ｒ０〜Ｒ１１は抵抗
、Ａは差動増幅器、Ｂはカレントミラ回路、Ｃはバイア
ス回路の各部分を示す。Figure 1 is a circuit diagram of a differential amplifier consisting of a conventional bias circuit, Figure 2 is a circuit diagram of a differential amplifier to which the bias circuit of this invention is applied, and Figure 3 is a circuit diagram of a differential amplifier using the bias circuit of this invention for demodulation of luminance signals. A circuit diagram when applied to a circuit is shown. In the figure, Q1 to Q8 are transistors, R0 to R11 are resistors, A is a differential amplifier, B is a current mirror circuit, and C is a bias circuit.
Claims (1)
差動増幅回路の出力端を直列接続した２個のＰＮ接合部
を負荷とするエミッタホロワトランジスタのベースに接
続し、前記２個のＰＮ接合部の接続点を、第１、第２の
トランジスタのベースに接続し、前記第１のトランジス
タを電子回路の、電流源とすると共に、第２のトランジ
スタのコレクタを前記差動増幅回路の他方の入力端に接
続したことを特徴とするバイアス回路。The output terminal of a differential amplifier circuit whose one input terminal is supplied with a reference voltage for bias is connected to the base of an emitter follower transistor whose load is two PN junctions connected in series. The connection point of the PN junction is connected to the bases of the first and second transistors, the first transistor is used as a current source of the electronic circuit, and the collector of the second transistor is connected to the bases of the first and second transistors. A bias circuit characterized in that it is connected to the other input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16023282U JPS5967018U (en) | 1982-10-25 | 1982-10-25 | bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16023282U JPS5967018U (en) | 1982-10-25 | 1982-10-25 | bias circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5967018U true JPS5967018U (en) | 1984-05-07 |
| JPS631454Y2 JPS631454Y2 (en) | 1988-01-14 |
Family
ID=30352483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16023282U Granted JPS5967018U (en) | 1982-10-25 | 1982-10-25 | bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5967018U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62165408A (en) * | 1986-01-17 | 1987-07-22 | Sony Corp | Fm demodulation circuit |
| JPS6398203A (en) * | 1986-10-15 | 1988-04-28 | Hitachi Ltd | Semiconductor integrated circuit |
| JP2007184688A (en) * | 2006-01-04 | 2007-07-19 | Fujitsu Ltd | Bias circuit |
-
1982
- 1982-10-25 JP JP16023282U patent/JPS5967018U/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62165408A (en) * | 1986-01-17 | 1987-07-22 | Sony Corp | Fm demodulation circuit |
| JPS6398203A (en) * | 1986-10-15 | 1988-04-28 | Hitachi Ltd | Semiconductor integrated circuit |
| JP2007184688A (en) * | 2006-01-04 | 2007-07-19 | Fujitsu Ltd | Bias circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS631454Y2 (en) | 1988-01-14 |
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