JPS595640A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS595640A JPS595640A JP57115115A JP11511582A JPS595640A JP S595640 A JPS595640 A JP S595640A JP 57115115 A JP57115115 A JP 57115115A JP 11511582 A JP11511582 A JP 11511582A JP S595640 A JPS595640 A JP S595640A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- conductive layer
- impedance matching
- semiconductor device
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01025—Manganese [Mn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置に関する。詳しくは、高速入力信号
に対し多重反射現象の釦生が防止されている半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device in which the phenomenon of multiple reflections is prevented for high-speed input signals.
（２）技術の背景
交流回路特に高周波回路においてインピーダンス整合が
必要であることは周知である。半導体装置を使用してな
す高周波回路においてもインピーダンス整合は必要であ
るが、半導体装置に含まれるそれぞれの能動素子、受動
素子は極めて微細であるから、半導体装置にインピーダ
ンス整合を施すことは必ずしも容易ではない。特に、ヒ
化ガリウム（ＧａＡｓ）等の化合物半導体を使用した電
界効果トランジスタによって構成された超高速論理集積
回路等において、多重反射にもとづく誤動作を防止する
ため、インピーダンス整合の問題は重要である。(2) Background of the Technology It is well known that impedance matching is necessary in AC circuits, especially in high frequency circuits. Impedance matching is also necessary in high-frequency circuits using semiconductor devices, but since each active element and passive element included in a semiconductor device is extremely minute, it is not necessarily easy to perform impedance matching on a semiconductor device. do not have. In particular, the problem of impedance matching is important in order to prevent malfunctions due to multiple reflections in ultra-high-speed logic integrated circuits configured with field effect transistors using compound semiconductors such as gallium arsenide (GaAs).
（３）従来技術と問題点
半導体装置におけるインピーダンス整合は、従来、第１
図に示す如き構成をもってなされていた。(3) Prior art and problems Impedance matching in semiconductor devices has traditionally been
It had a configuration as shown in the figure.
すなわち、接地された固定抵抗Ｒを入力端子と並列に接
続するものである。図において、１は半導体チップであ
り、２は絶縁体から構成される半導体装置パッケージの
基体である。また３は導電層パターンであり、４は外部
接続端子であり、５はボンディングワイヤである。また
６はプリント基板７上に形成された高速信号入力ブスで
あり、８はインピーダンス整合用終端抵抗、９は前記プ
リント基板７上に形成された接地用導電層Ａターンであ
る。前記半導体装置並フびに終端抵抗８は該プリント基
板７上に載置され、終端抵抗８はボンディングワイヤ１
０．１０’によって信号入力ブス６及び接地用導電層パ
ターン９に接続される。すなわち、入力ブス６と外部接
続端子４との接続点に終端抵抗８が接続されている。こ
のような従来技術における構成によっては、人カブスフ
と外部接続端子４との接続点より入力側の区間における
人力信号パルスの反射は防止しうるが、この接続点より
出力側、つまり、パッケージ２内に設けられている導電
層パターン２やボンディングワイヤ５等における入力信
号パルスの反射は防止することができない。特に、パッ
ケージ２がセラミックパッケージである場合は、導電層
パターン３における信号伝播速度が遅くなり、入力信号
パルスのパルス周波数が高いときは多重反射を惹起しや
すい。換言すれば、もし、パッケージ基体２を構成する
セラミック材がアルミナ（Ａ１２０３）であると、アル
ミナ（Ａ１２０３）の比誘電率（ε）は９．６であり、
信号伝播速度はＦに比例するから、導電パターン倍の時
間を要することになる。そのため、導電層パターン３の
電気長は実長の約３倍に延長される結果となる。例えば
、導電層パターン３の実際の長さが約１ （＋ｎ ＋
ｎ ）であると仮定すると電気長は３〔１旧ｎ〕となり
、信号がこの導電層パターン３を通過する時間は約１０
（ｐｓ）となり、２０（ｐｓ）程度の時間間隔をもって
信号パルスは反射し、多重反射現象を呈することになる
。That is, a grounded fixed resistor R is connected in parallel with the input terminal. In the figure, 1 is a semiconductor chip, and 2 is a base of a semiconductor device package made of an insulator. Further, 3 is a conductive layer pattern, 4 is an external connection terminal, and 5 is a bonding wire. Further, 6 is a high-speed signal input bus formed on the printed circuit board 7, 8 is a terminating resistor for impedance matching, and 9 is an A-turn of a grounding conductive layer formed on the printed circuit board 7. The semiconductor device and the terminating resistor 8 are mounted on the printed circuit board 7, and the terminating resistor 8 is connected to the bonding wire 1.
It is connected to the signal input bus 6 and the grounding conductive layer pattern 9 by 0.10'. That is, a terminating resistor 8 is connected to the connection point between the input bus 6 and the external connection terminal 4. Depending on the configuration in the prior art, it is possible to prevent reflection of the human power signal pulse in the section on the input side from the connection point between the human cubboard and the external connection terminal 4, but on the output side from this connection point, that is, inside the package 2. It is not possible to prevent the input signal pulse from being reflected on the conductive layer pattern 2, bonding wire 5, etc. provided on the substrate. In particular, when the package 2 is a ceramic package, the signal propagation speed in the conductive layer pattern 3 is slow, and multiple reflections are likely to occur when the pulse frequency of the input signal pulse is high. In other words, if the ceramic material constituting the package base 2 is alumina (A1203), the dielectric constant (ε) of alumina (A1203) is 9.6,
Since the signal propagation speed is proportional to F, it will take twice as much time as the conductive pattern. Therefore, the electrical length of the conductive layer pattern 3 is extended to about three times its actual length. For example, the actual length of the conductive layer pattern 3 is about 1 (+n +
n ), the electrical length is 3 [1 old n], and the time it takes for a signal to pass through this conductive layer pattern 3 is approximately 10
(ps), and the signal pulse is reflected at a time interval of about 20 (ps), resulting in a multiple reflection phenomenon.
この多重反射の問題は、スイッチング速度が比較的遅い
場合はそれ程重大な問題とはならないが、例えばヒ化ガ
リウム（Ｇａ Ａｓ）等の化合物半導体を使用した電界
効果トランジスタによって構成された超高速論理集積回
路等スイッチング時間が１００ｒｐｓｌ程度であるもの
に対しては十分誤動作の原因となり、重大な欠点となる
。This problem of multiple reflections is not a serious problem when the switching speed is relatively slow, but for example, in ultra-high-speed logic integrated circuits made of field-effect transistors using compound semiconductors such as gallium arsenide (GaAs). For circuits with a switching time of about 100 rpsl, this can cause malfunctions, which is a serious drawback.
（４）会も明の目的
本発明の目的は、Ｃの欠点を解消することにあり、数Ｇ
Ｈ２以上の高速入力信号に対し多重反射現象の光生が防
止されている半導体装置を提供することにある。(4) Purpose of the present invention The purpose of the present invention is to eliminate the drawbacks of C,
It is an object of the present invention to provide a semiconductor device in which light generation due to multiple reflection phenomenon is prevented for high-speed input signals of H2 or higher.
（５）発明の構成
本発明によれば、絶縁基板と該絶縁基板上に載置された
半導体素子と、該半導体素子周囲の絶縁基板上１こ配設
された複数の導電層とを備え、前記半導体素子の入力端
子に接続される第１の導電層が、終端抵抗に接続される
第２の導電層に電気的に接続されてなることを特徴とす
る半導体装置が提供される。(5) Structure of the Invention According to the present invention, an insulating substrate, a semiconductor element placed on the insulating substrate, and a plurality of conductive layers disposed on the insulating substrate around the semiconductor element, A semiconductor device is provided, wherein a first conductive layer connected to an input terminal of the semiconductor element is electrically connected to a second conductive layer connected to a terminating resistor.
本発明は、上記の多重反射現象の釦主の原因が、終端抵
抗の接続される位置の選択が必ずしも適当でないことに
ある点に着目して、終端抵抗を第２図の等価回路に示す
位置に終端抵抗を移動することとしたものである。第２
図において、ｚｌは入力端のインピーダンスであり、Ａ
２は導電パターン３のインピーダンスであり、几は終端
抵抗７であり、９は高速入力信号の入力されるポンディ
ングパッドである。このような接続となすことにより一
点鎖線１０によって囲まれるパッケージ内において多重
反射は発生せず、人力パルス信号は終端抵抗７で吸収さ
れることになる。The present invention focuses on the fact that the main cause of the above-mentioned multiple reflection phenomenon is that the selection of the position where the terminating resistor is connected is not necessarily appropriate, and the terminating resistor is connected at the position shown in the equivalent circuit of Fig. 2. The terminating resistor was moved to Second
In the figure, zl is the impedance at the input end, and A
2 is the impedance of the conductive pattern 3, 几 is the terminating resistor 7, and 9 is a bonding pad to which a high-speed input signal is input. By making such a connection, multiple reflections will not occur within the package surrounded by the dashed line 10, and the human pulse signal will be absorbed by the terminating resistor 7.
（６）発明の実施例
以下、図面を参照しつつ、本発明の一実施例にかかる半
導体装置について説明し、本発明の構成と特有の効果と
を明らかにする。(6) Embodiment of the Invention Hereinafter, a semiconductor device according to an embodiment of the invention will be explained with reference to the drawings, and the structure and unique effects of the invention will be clarified.
第３図は本発明の一実施例に係る、セラミックパッケー
ジに素子が封入されてなる半導体装置において、高速人
力信号入力端子部とインピーダンス整合部とを示した図
である。図において、１．２．３．４．５．６．７．８
．９．１０．１０′は、第１図に示Ｖところと同様、そ
れぞれ、半導体チップ、半導体装置用セラミックパッケ
ージ基体、導電層パターン、外部接続端子、ボンディン
グワイヤ、高速信号入カブス、プリント配線板インピー
ダンス整合用終゛端抵抗、接地用導電層パターン、ボン
ディングワイヤである。導電層パターン３はパッケージ
２のセラミック基体の表面にモリブデン、マンガン（Ｍ
ｏ −Ｍｎ ）をメタライズして形成すれており、その
一端にはコバール製外部接続端子４がろう付けされ、導
電層パターン３と外部接続端子４とは金メッキされてい
る。３と４とは、それぞれ、インピーダンス整合用の導
電層パターンと外部接続端子とであり、インピーダンス
整合用端子を構成し、その１端は終端抵抗７に接続され
、他端はボンディングワイヤ５′を介して半導体チップ
１の人力信号用ポンディングパッド１０に接続される。FIG. 3 is a diagram showing a high-speed human input signal input terminal section and an impedance matching section in a semiconductor device in which an element is enclosed in a ceramic package according to an embodiment of the present invention. In the figure, 1.2.3.4.5.6.7.8
．． 9.10.10' are the same as shown in Figure 1, respectively: semiconductor chip, ceramic package substrate for semiconductor device, conductive layer pattern, external connection terminal, bonding wire, high-speed signal input cube, printed wiring board impedance. These are a matching termination resistor, a grounding conductive layer pattern, and a bonding wire. The conductive layer pattern 3 includes molybdenum and manganese (M) on the surface of the ceramic substrate of the package 2.
The conductive layer pattern 3 and the external connection terminal 4 are plated with gold, and the external connection terminal 4 made of Kovar is brazed to one end thereof. 3 and 4 are a conductive layer pattern and an external connection terminal for impedance matching, respectively, and constitute an impedance matching terminal, one end of which is connected to the terminating resistor 7, and the other end of which is connected to the bonding wire 5'. It is connected to the human input signal pad 10 of the semiconductor chip 1 through the connector.
以上の構成によって、第２図に示す等価回路が実現され
る。すなわち、高速信号人力はパッケージ内において多
重反射されることなく、終端抵抗７の中で吸収される。With the above configuration, the equivalent circuit shown in FIG. 2 is realized. That is, the high-speed signal power is absorbed within the termination resistor 7 without being subjected to multiple reflections within the package.
なお、本発明の池の実施例によれば、第４図に示される
如く導電層パターン３．３′間をボンディングワイヤ５
番こよって直接接続しても実用上さしつかえない。According to the embodiment of the present invention, a bonding wire 5 is connected between the conductive layer patterns 3 and 3' as shown in FIG.
There is no practical problem even if you connect directly depending on the number.
又、本発明が論理回路のみならず、リニヤ回路にも適用
しうることはいうまでもない。Furthermore, it goes without saying that the present invention can be applied not only to logic circuits but also to linear circuits.
（７）発明の詳細
な説明せるとおり、本発明によれば、ＧＨ２以上の高速
人力１こ対し多重反射現象の発生が防止さ(7) As explained in detail, according to the present invention, the occurrence of multiple reflection phenomenon in response to high-speed human power of GH2 or higher is prevented.
第１図は従来技術における半導体装置のインピーダンス
整合部の模式的構造図である。第２１劇は発明の技術的
思想を説明するブロック図である。
第３図及び第４図は本鈍明の実施例に係る半導体装置の
インピーダンス整合部の構造を示す平面図である。
１・・・・・・半導体チップ、２・・・・・・半導体装
置パッケージ、３・・・・・・導電層パターン、４・・
・・・・外部接続端子、５・・・・・・ボンディングワ
イヤ、６・・・・・・信号入力ブス、７・・・・・・プ
リント配線板、８・・・・・・インピーダンス整合用接
地抵抗（終端抵抗）、９・・・・・・接地用導電層パタ
ーン、１０・・・・・・入力信号の入力されるポンディ
ングパッド、３′・・・・・・インピーダンス整合用導
電層パターン、４′・・・・・・インピーダンス整合用
外部接続端子、５′、５″・・・・・・インピーダンス
整合用ホンディングワイヤ、Ｚｌ・・・・・・入力端イ
ンピーダンス、ｚ２・・・・・・導電層パターンのイン
ピーダンス。
Ｌｒ′−Ａ・］FIG. 1 is a schematic structural diagram of an impedance matching section of a semiconductor device in the prior art. The 21st play is a block diagram explaining the technical idea of the invention. 3 and 4 are plan views showing the structure of an impedance matching section of a semiconductor device according to an embodiment of the present invention. 1... Semiconductor chip, 2... Semiconductor device package, 3... Conductive layer pattern, 4...
...External connection terminal, 5...Bonding wire, 6...Signal input bus, 7...Printed wiring board, 8...For impedance matching Grounding resistor (terminal resistor), 9... conductive layer pattern for grounding, 10... bonding pad to which input signal is input, 3'... conductive layer for impedance matching Pattern, 4'...External connection terminal for impedance matching, 5', 5''...Honding wire for impedance matching, Zl...Input end impedance, z2... ... Impedance of the conductive layer pattern. Lr'-A.]
Claims (1)
半導体素子周囲の絶縁基板上に配設された複数の導電層
とを備え、前記半導体素子の入力端子に接続される第１
の導電層が、終端抵抗に接続される第２の導電層に電気
的に接続されてなることを特徴とする半導体装置。A first semiconductor device comprising an insulating substrate, a semiconductor element placed on the insulating substrate, and a plurality of conductive layers disposed on the insulating substrate around the semiconductor element, and connected to an input terminal of the semiconductor element.
A semiconductor device characterized in that the conductive layer is electrically connected to a second conductive layer connected to a terminating resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57115115A JPS595640A (en) | 1982-07-01 | 1982-07-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57115115A JPS595640A (en) | 1982-07-01 | 1982-07-01 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS595640A true JPS595640A (en) | 1984-01-12 |
| JPH0423827B2 JPH0423827B2 (en) | 1992-04-23 |
Family
ID=14654609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57115115A Granted JPS595640A (en) | 1982-07-01 | 1982-07-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS595640A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01180813A (en) * | 1988-01-12 | 1989-07-18 | Shiseido Co Ltd | Hair cosmetic |
| JPH02501350A (en) * | 1987-01-02 | 1990-05-17 | インジエクト スター ペケルマシネン ゲゼルシヤフト エム．ベー．ハー． | Device that separates pieces of meat attached to bones |
| US5393521A (en) * | 1989-12-21 | 1995-02-28 | Dep Corporation | Hair treatments utilizing polymethylalkylsiloxanes |
| DE19712292A1 (en) * | 1997-03-24 | 1998-10-01 | Deutsch Zentr Luft & Raumfahrt | Flange unit for active vibration suppression |
-
1982
- 1982-07-01 JP JP57115115A patent/JPS595640A/en active Granted
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02501350A (en) * | 1987-01-02 | 1990-05-17 | インジエクト スター ペケルマシネン ゲゼルシヤフト エム．ベー．ハー． | Device that separates pieces of meat attached to bones |
| JPH0411178B2 (en) * | 1987-01-02 | 1992-02-27 | ||
| JPH01180813A (en) * | 1988-01-12 | 1989-07-18 | Shiseido Co Ltd | Hair cosmetic |
| JP2554514B2 (en) * | 1988-01-12 | 1996-11-13 | 株式会社資生堂 | Hair cosmetics |
| US5393521A (en) * | 1989-12-21 | 1995-02-28 | Dep Corporation | Hair treatments utilizing polymethylalkylsiloxanes |
| DE19712292A1 (en) * | 1997-03-24 | 1998-10-01 | Deutsch Zentr Luft & Raumfahrt | Flange unit for active vibration suppression |
| DE19712292B4 (en) * | 1997-03-24 | 2004-12-02 | Deutsches Zentrum für Luft- und Raumfahrt e.V. | vibration |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0423827B2 (en) | 1992-04-23 |
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