JPS59188159A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the high temperature characteristics of a semiconductor device by providing opposite electrodes (cathode) of a Schottky barrier directly on a high density buried layer, thereby largely reducing a series resistance. CONSTITUTION:In order to reduce the series resistance of a Schottky barrier diode, an n<-> type Si layer 3 is selectively etched to form a recess, B ions are selectively implanted, a p type isolation region 12 connected to a p type substrate 1, a guard ring of the diode, a p type region 13a to become the base of a low withstand voltage n-p-n type transistor, and a p type region 13b to become the base of a high voltage transistor. As ions are implanted to form an n<+> type region 15a to become the base of a low withstand voltage transistor, an n<+> type region 15b to become an emitter of a high withstand voltage transistor, a high density n<+> type region 16 on the surface of an n<+> type buried layer 2 as a cathode contact of the diode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device equipped with a Schottky barrier.

[Background technology]

When forming a Schottky barrier diode as part of a semiconductor integrated circuit device (IC, LSI), as shown in FIG. After epitaxially growing the n-type Si layer 3, A4 is deposited on a part of the surface of the n-type Si layer in the island region where the n-type Si layer is separated from other regions by the p-type diffusion layer 4, etc.
A Schottky barrier electrode (anode) A is formed by vapor-depositing a metal such as A, a Schottky barrier electrode (anode) A is formed in the other part of the n-type Si layer, and a high concentration meter type diffusion layer 5 is formed, and a second electrode is ohmically connected to this n-type diffusion layer 5. (Kando) K is provided. By the way, if left as is, the series resistance in the Schottky barrier diode will be increased by the epitaxial n-type layer, which is unfavorable in terms of high temperature characteristics. Therefore, n+ type diffusion M5
A deep high concentration n-type diffusion layer (referred to as a CN-1-1 row) 6, which is used for the collector extraction portion of the transistor, is formed on the n-10V implanted layer 2. There is. However, 51〈The diffused CN ten layer 6 is also diffused in the horizontal direction at the same time. No, no.

[Purpose of the invention]

The present invention has been made to improve the above-mentioned points, and its purpose is to improve the degree of integration and high temperature characteristics of a semiconductor device having a Schottky barrier.

[Summary of the invention]

In order to achieve the object 1-, the present invention has the following features:
As shown in the specific example, a recess 7 reaching from the surface to the buried layer 2 is formed on the cathode side of the semiconductor island region 3 where the Schottky barrier is formed, and a counter electrode (cathode) of the Schottky barrier is directly formed in this high concentration buried layer 142. By providing Kk,
This significantly reduces series resistance.

When forming a recessed part by etching a semiconductor single crystal hanger, for example, an anisotropic etching technique using alkaline or F liquid is used.
By adopting this method, a deep recess with a steep slope can be obtained in a relatively small area, and it will not spread laterally as in the case of conventional CN-10 diffusion, and will improve the degree of integration. It's advantageous. According to the present invention, at least the cathode side of the Schottky barrier diode does not have an epitaxial n-type layer and is in direct contact with the n-type buried layer, so that the series resistance is significantly reduced and it can withstand high temperatures. Also, the characteristics of the device in the high current region are improved without deteriorating the circuit operation margin.

〔Example〕

Figures 31 to 7 are cross-sectional views of the main culms of the prosthene of the embodiment in which the present invention is applied to an IC having a transistor with a Schottky barrier diode (including I2L in this case), and shows The details will be explained according to each I culm.

(1) As shown in FIG.
A substrate epitaxially grown to a thickness of ~2 μm is prepared. The n++ buried layer 2 is buried in a plurality of locations corresponding to the elements to be formed thereon.

(2) As shown in FIG. 4, a part of the surface of the I/Cn-type Si layer 3 is masked with a Sin film 8, etc. to form a part that will become a Schottky barrier diode, an isolation part that separates the elements, and an I2L element. A recessed portion 9 is formed by selectively etching the portion to a depth of approximately 1 μm.

(3) Furthermore, as shown in Fig. 5, in order to shorten the diffusion time for forming the isolation region and to reduce the series resistance of the Schottky barrier diode, a part of the surface of the n-type Si layer 3 is New 5in2 membrane 8
' is used as a mask to selectively etch to form a recessed portion 10.

(4) As shown in FIG. 6, using the 5in2 film 11 formed on the surface of the n-type Si layer in the recessed portion 10 as a mask, B (boron) ions are selectively applied to the isolation portion between each element. p-type (isolation) region 1 connected to p-type substrate by implantation and stretching diffusion
At the same time, a P-type region 13a which becomes a guard ring of a Schottky barrier diode and a base of a low breakdown voltage npn transistor and a p-type region 13b which becomes a base of a high breakdown voltage transistor are formed.

Note that in this step, although not shown in the figure,
In other island regions, p becomes the injector of I2L.
A type region and a p-type region (partially shown) which will serve as a base for an npn inverse transistor are formed at the same time.

(5) As shown in FIG. 7, the SiO2 film 11 on the surface
′ as a mask, by implanting (or depositing) As ions and diffusing n, which will become the emitter of the low voltage transistor.
+ type region 15a, n+ type region 15b which becomes the emitter of the high voltage transistor, and furthermore, a high concentration n+ type region 6 on the surface of the n++ buried layer as the cathode contact part of the Schottky barrier diode, and although not shown in the figure, the I''L At the same time, an n+ type region that will become the multi-collector of the inverse transistor is formed.

After that, a bancivation film is formed on one surface using PSG or the like, and after contact photoetching, Ap is evaporated and wiring patterns are etched to form electrodes (wirings) that contact each area.
form.

FIG. 9 shows the configuration of an npn (npn) transistor, an I2L transistor, and a Schottky barrier transistor formed on one substrate according to the above process.

FIG. 8 is a circuit diagram equivalent to the Schottky barrier transistor shown in FIG. 9.

[Effect. Fruit]

As described above in the examples, in the I2L coexistence type microprocess, by etching the surface of the n-type Si layer to a certain depth in the isolation region and the I2L region, it is possible to In addition to being able to prevent diffusion to , the β1% property of I2L can be improved. Therefore, by exposing the N++ buried layer by etching the collector contact part of a transistor with a Schottky barrier diode, it is possible to simultaneously realize a structure that reduces the series resistance on the cathode electrode side, and also eliminates the need for diffusion to take out the collector. .

The only way to reduce the resistance of a Schottky barrier diode is to increase the element size without adding a process or improving the vertical structure, but if you follow the above plan, you can ignore the resistance directly across the collector and F without adding any process. This reduces the series resistance of the Schottky barrier diode, requires less silencing power during one-time operation, and improves temperature characteristics.

[Application field]

The present invention is effective when applied to an IC inside a high frequency element.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view showing an example of a Schottky barrier diode. FIG. 2 is a longitudinal sectional view showing the principle structure of a Schottky barrier diode according to the present invention. Figures 31 to 7 are cross-sectional views showing one embodiment of the process for manufacturing a transistor with a Schottky barrier diode according to the present invention. No. 81A is an equivalent circuit diagram of a transistor with a Schottky barrier diode. FIG. 9 is a longitudinal sectional view showing an IC incorporating a Schottky barrier diode according to the present invention. 1. P-type Si substrate, 2-. N-type buried layer, 3. Epitaxial n-type Si layer, 4. Isolation p-type layer, 5. N+-type scattering layer 6-.n Type well (CN+)
, 7. Concave portion, 8. - Si02 film, 9... Shallow recess, 10. Deep recess, 11, 11', SiO2 film, 12. - p-type well, 13a, 13b-p-type region,
15a, 15b, 16-n+ type region Fig. 1 Fig. 2 Fig. 3 Fig. 4

Claims (1)

[Claims] 1. In a semiconductor device in which a Schottky barrier is formed on a part of the surface of a semiconductor substrate having a high concentration buried layer, a recess is formed in another part of the semiconductor substrate, and A semiconductor device characterized in that a counter electrode of a Schottky barrier is directly provided in the semiconductor substrate. Claim 3: Elements such as transistors are formed at a plurality of locations on the semiconductor, and each element is electrically separated by a recessed portion and a conductivity type V having a different conductivity from the base. In this patent, a counter electrode of the Schottky barrier is provided in a part of the iC recess. An old conductor device according to claim 1 or 2.