JPS5917724A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make the operation high-speed and reduce the power consumption, by performing logical operations including NAND and AND only with gates having the same input level in a current switching logic circuit constituted with field effect transistors. CONSTITUTION:Only when signals A and B of input terminals 33 and 34 are in the level L, a current is flowed to resistances R31 and R32, and as the result, ANDA.B between two inputs A and B is obtained in an output terminal 38, and NANDA.B between two inputs A and B is obtained in an output terminal 39. Actions for outputs of two inputs A and B are the same, and their input levels and noise margins are the same. As the result, the logical amplitude can be made shorter, and operations of the logic integrated circuit are made in a high- speed, and the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, particularly a field effect transistor (hereinafter referred to as MESFET) with a Schottky junction as a gate.
In a current-switching logic circuit consisting of
The present invention relates to a field effect transistor circuit capable of performing logical product operations with excellent noise margin.

First, regarding this type of conventional technology, logic integrated circuits using compound semiconductors such as gallium arsenide are attracting attention due to society's demand for higher speed information processing. 1. MESFETs (field effect transistors with a Schottky junction as a gate) are the mainstream transistors used in compound semiconductor integrated circuits because they are easier to manufacture than other transistors.

However, MESFETs have a problem in that the threshold voltage of the channel changes significantly depending on the thickness of the active layer that serves as the channel. For example, in an active layer of gallium arsenide with a gearia concentration of 10 cm 2 , if the thickness changes by 70%, the gate threshold voltage will change by 0. It is very difficult to uniformly control all the threshold voltages of MESFETs in Ueno to around oV.

Therefore, the present inventors used a differential amplifier circuit to
We have developed logic circuits that can eliminate the contribution of FET threshold voltages to logic input levels.

The conventional technology is NAND/AN including this type of differential amplifier circuit.
When applied to the D game path, the circuit shown in FIG. 1 is obtained. Referring to the figure, 11 is a power supply voltage terminal, and 12 is a ground terminal. MESFETQ11'Q12 are connected in series and their gates are connected to input terminals 13 and 14, respectively.
shall be. The gate of MESFETQ13 is the reference voltage terminal 15.

The source terminals of MESFETs Q12 and Q13 are connected in common, and a current source 16 is inserted between them and the ground terminal 12. Resistor R111R12 is MESFETQ, 1°Q13
is the load resistance. MESFETQ14 is the source
Diode D acts as a follower and for level shifting
, a resistor R13 is connected in series with the ground terminal 12. MESFETQ*5 is also a source
Diode D1 acts as a follower and for level shifting
2. A resistor R14 is connected in series with the ground terminal 12. The output is obtained from output terminals 17.18.

In this circuit, current flows through the resistor R11 only when both input terminals 13 and 14 are at the rHJ level, so the output terminal 17 provides a two-person NAND, and the output terminal 18 provides an AND. .

However, in these two-man powered NAND and AND gates, the input characteristics of the input terminals 13 and 14 are not completely the same, and the second
There are differences in the input transfer characteristics as shown in the figure. Here the second
In the figure, A and B are input signals to terminals 13 and 14, respectively, and F is a signal to output terminal 17. The solid line is the result when input signal A is fixed at the "H" level and input signal B is varied.

At this time, the output signal F changes using the reference voltage REF as the threshold value of the input signal.

On the other hand, the broken line shows the result when the input signal B is fixed at the rHJ level and the input signal A is varied.

The slope of the transfer characteristic is not as steep as the solid line, the r Hj r L j levels of the input signal require a large level difference, and the noise margin of the input signal is reduced. Furthermore, the threshold value of the input signal changes depending on the rHJ level of signal B rather than vREF. In this way, the reason why the transfer characteristic from input terminal 13 is inferior to that from input terminal 14 is that when a signal is applied from input terminal 13, MESFETQ, 12
This is because the on-resistance of MESI"ETQll acts as the source resistance of MESI"ETQll, and the mutual conductance apparently decreases.

Also, due to the presence of the on-resistance of MESFETQ12, MESFET
SFETQll, Q12. The differential circuit consisting of Q13 becomes asymmetrical, and as a result, the threshold of the signal A at the input terminal 13 becomes higher than the reference voltage REF, resulting in the inconvenience that the reference voltage of the signal A cannot be determined unambiguously. occurs. Therefore, in this circuit, it becomes necessary to apply a signal with a sufficiently large logic amplitude to the input, resulting in a slowdown in calculation speed and an increase in power consumption.

The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to create a current-switching NAND circuit using MESFETs that have the same transfer characteristics from each input gate and have excellent noise margins. It provides an AND game path.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to the present invention will be explained in detail below based on an embodiment of a field effect transistor circuit with reference to the drawings. FIG. 3 is a circuit showing a first embodiment of the present invention. Terminal 31 is a power supply voltage terminal, and terminal 32 is a ground terminal. M, ESFET Q31 and Q32' Q33 and Q34 each form a differential amplifier circuit. M.E.
The gate terminal of SFETQ31 is set as input terminal 33, and M
The gate terminal of ESFETQ34 is designated as input terminal 34. The respective gates of MESFETQ32°Q33 are connected in common and used as a reference voltage terminal 35. MESFETQ31.
The sources of Q32 are commonly connected and connected to a current source 36. IVIEsFETQ33. The sources of Q34 are commonly connected and connected to a current source 37. Load resistance R31'R3
2 are MESFETQ31. It is connected between the drain terminal of Qs2 and the power supply terminal 31. Load resistance R3
3 is MESFETQ32. It is connected between the common connection terminal of the drain of Q33 and the power supply terminal 31. Furthermore, MES
FETQ, common drain of 32, 33 and MESFETQ
A diode D31 and a resistor R14 are connected in series to the source of MESFET Q35, and connected to the ground terminal 32.

MESFETQ31. M on each drain of Q34
ESFETQ36. Connect each gate of Q3□ and ME
SFETQ36. The sources of Q3□ are connected in common, and a diode I) 32 and a resistor 35 are connected in series between the sources of Q3□ and the ground terminal 32. It is obtained from output terminals 38 and 39.

In such a circuit configuration, the resistor R3312@ current flows only when the signals at the input terminals 33 and 34 are both at the rLJ level, and as a result, a two-way AND signal is obtained at the output terminal 38. Since the output of the output terminal 39 is at the rHJ level if at least one of the two power sources is at the rLJ level, a two-man power NAND is obtained. In other words, if the signals at the input/terminals 33 and 34 are A and B, respectively, then the signals at the output/terminals 38 and 39 are A-I3 and A-, respectively.
B is obtained. According to this circuit, the effects on the output of the two human forces A and B are completely equal, and the input level and noise margin are also the same.

As a result, it is possible to reduce the logic amplitude, and therefore, it is possible to reduce the power consumption by increasing the speed of the logic integrated circuit.

FIG. 4 is a circuit showing a second embodiment of the present invention, which constitutes a half adder. The circuit surrounded by the broken line is the circuit shown in the first embodiment of the present invention. MESFET
Q48. C49 and MESFETQ41, C4 respectively
4 and connect in parallel, with common drain and north. The gates of ME S I" E TQ48°C49 are input terminals 410 and 411, respectively. Input terminal 43
, 410, 44, 411 have human input signals A, B, λ
, If you include misfortune, MESF ETQ41, Q42+Q
410 and Q 43 + Q 44wQ411, l
: t-t#'L that A, B and λ, T3(7)N
OR.

A 0'R operation is performed. As a result, a half-added output AB+λB of A and H is obtained at the output terminal 48, and the output terminal 4
9, an output of AB+λ×100 is obtained by inverting AB+λB. Since all of these four inputs have the same electrical characteristics, the required rHJrLj level may also be the same. As a result, the noise margins of the input gates are all equal, so the logic amplitude within the integrated circuit can be minimized, thereby increasing the calculation speed and reducing power consumption.

FIG. 5 shows a third embodiment of the present invention, which is a circuit for calculating majority logic. The circuit surrounded by a broken line is the circuit shown in the second embodiment of the present invention. MESFET
The drain and source of Q51o are commonly connected to MESFET Q59, and the gate is used as an input terminal 512. M.E.
The respective gates of SFETQ5111Q512゜C513 and C514 are connected to input terminals 513, 514, 515
and O MESFETQ51 as reference voltage terminal 65.
1, the sources of C512, C513, and C514 are commonly connected, and a current source 516 is connected between them and the ground terminal 52.

The drains of the MESFETs Q511°C512' and C513 are commonly connected, and a resistor R56 is inserted between them and the drain power supply terminal. Furthermore, MESFETQ511,C
512+Q513 common drain to MESFETQ
515, and further connected to the gate of MESFETQ5. ,
connects the drain and source in parallel with MESFETQ5□. The drain of MESFETQ514 is MESF'E
TQ62. Commonly connected to the drain of C53. In this circuit, input terminals 53, 54, 510, 511 . 512
, 513° 614, , 515 respectively have signals A, A,
B.■.

When C1λ, B, and C are applied, F=(
A+B) (A100C) (λ+B +C)-AB +BC
(-CA majority logic is obtained.Similarly, the output terminal 59
The inversion of F is obtained as P = λn + λd + Cλ. Since all the input terminals have the same electrical characteristics, the logic amplitude applied to the input terminals can be minimized. As a result, it is possible to increase the logical operation speed and reduce power consumption.

In this way, with the semiconductor integrated circuit according to the present invention,
NAND-A with only gates with equal input signal levels
It is possible to perform ND and logical operations including these. As a result, the logic amplitude of the input signal can be kept to the minimum necessary, thereby increasing the calculation speed and achieving a low power consumption ratio.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional AND/AND-NAND operation according to the first embodiment of the present invention using a differential amplifier circuit;
The figure is a half-adder circuit diagram of a second embodiment of the present invention, and FIG. 5 is a circuit diagram of majority logic operation of a third embodiment of the present invention. 11.31.41, E51...Power terminal,
12゜32, 42, 52 ・-・-Earth☆1iii
"'T", 13,14°3'3,34,43,44,4
10,411,53゜54.510,511.512,
513,514゜515... Human power terminal; child, 1, 35, 45, 65... Reference voltage terminal,
16, 36, 37, 46. 47.56,57,516...Current source, 1γ. 18.38.39.48.49.58.69...
・Output terminal P, Q11 to Q15. Q31~Q3□, Q41
~Q49゜Q51~Q514...M b S
FET-, R11~lN14゜R-R, R-R, R
-R・・・Resistance, 31 35 41
45 51 56■]11. D12. D31
．． D32. D41. ■)42. D511D62...
··diode. Name of agent: Patent attorney Toshio Nakao and 1 other person i1
Figure 2 Figure 2 Input constant pressure m3 Figure 4

Claims (1)

[Claims] In a logic circuit in which a current switching logic is configured using a differential amplifier circuit using a Schottky junction Guth type field-of-mind effect transistor made of a compound semiconductor, two differential amplifier circuits are used for current switching, and two on the reference side are used. 1. A semiconductor integrated circuit characterized in that the drains of two transistors are connected in common, and the sources of source follower transistors receiving the drain outputs of two input side transistors are connected in common.