JPS59168995A - Memory - Google Patents

Abstract

PURPOSE:To perform actual operation test of a memory simply without adding excessive input/output signal terminals for test by constituting a memory testing circuit provided with a timing generating circuit and an oscillator on the same semiconductor substrate with the memory. CONSTITUTION:A testing circuit 11 is connected to a starting signal line 12 for the purpose of testing memory 2. A mode selecting signal line 13 switches selectors 9a, 9b at the time of testing and connects a group of signal lines between the memory 2 and a testing circuit 11. An error detecting signal line 14 tests the memory 2 by the testing circuit 11 and reports presence of malfunction. One of output signal line 15 for the memory 2 sends out the output signal of the memory 2 normally, and sends out an error detection signal at the time of testing. One input terminal for a starting signal line 12 is enough for signal terminal increased at this time. As the testing circuit 11 has a built-in oscillator 16, it is not necessary to give clock. The memory 2 and testing circuit are constituted on the same semiconductor substrate.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a storage device that is a component of an information processing device such as an electronic computer, and more specifically, to a storage device that is a component of an information processing device such as an electronic computer. , relates to memory devices constructed on the same semiconductor substrate.

[Prior art]

Conventionally, many of these types of storage devices have been implemented as a basic unit, such as a package, which has a dedicated storage function. In other words, it is a closed device as a storage circuit (hereinafter referred to as memory). Further, even when a memory and other logic circuits are combined on the same semiconductor substrate, there is no example in which a test circuit is incorporated internally independently of these logic circuits.

In general, there are various ways to test memory.
It is effective to increase the operating speed to the full capacity of the memory, run a test pattern specific to the memory, and examine its response. To test these memories, it is necessary to use a dedicated memory testing device.

FIG. 1 is an explanatory diagram showing a method of testing a single memory. In FIG. 1, (1) is a memory test device, (2
) is a memory, (3) is a storage device incorporating memory (2), (4) is a group of input signal lines to memory (2), and (5) is a group of output signal lines from memory (2).

The above method is used to test a single memory, but in the case of a device with memory embedded inside, in order to effectively test the memory, it is necessary to connect the test signal between the external memory test device and the memory in advance. It is necessary to dose the routes and terminals.

FIG. 2 is an explanatory diagram showing a method of testing a device with embedded memory. In Figure 2, (6) is the memory (2
), the logic circuit (7) is incorporated with the logic circuit (6
) to the memory (2), and (8) conversely shows a group of connection signal lines from the memory (2) to the logic circuit (6).

In this case, external memory test equipment (1) and memory (2)
), the memory (2) cannot be tested if the test signals ltM group (4), (5) are #f.

FIG. 3 is a configuration diagram in which a test signal path is provided in the case of FIG. 2. In FIG. 3, (9a) is the input signal line group (4) from the outside to the memory (2) and the internal logic circuit (6).
) to the connection signal line group (7) to the memory (2) (hereinafter referred to as selector), (9b)
is a selector for switching with the intermediate output signal line group in order to output the output signal line group (5) from the memory (2) to the outside;
αO indicates a switching signal line that provides the switching signal.

By such means, the memory (2) was tested by an external memory test device ().

Since conventional storage devices were configured as described above, in order to test the actual operating speed of the memory, it was necessary to connect with an external memory testing device.

In addition, in the case of a closed storage with a single memory, it is possible to test the single memory as described above, but in the case of a device with built-in memory, a path and terminal must be prepared to test the memory as described above. I had to.

As the degree of integration of devices increases, the number of input/output terminals tends to increase, and as this is becoming an impediment to increasing the degree of integration, it will become increasingly difficult to provide terminals for testing internal memory. It's coming.

(2) Therefore, in the case of a device with a built-in memory that cannot have a test terminal, it is not possible to perform a sufficient test at actual operating speed.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above.It incorporates a memory test circuit together with a memory, and by giving a start code to the test terminal, it can perform a series of tests by itself. The purpose is to provide a storage device that can output only the results.

[Embodiments of the invention]

An embodiment of the present invention will be explained below with reference to the drawings. Fourth
The figure is a configuration diagram of an embodiment of a storage device according to the present invention. In FIG. 4, (U+ is a test circuit for testing the memory (2), α4 is a start signal line of the test circuit α1:
α4 is a mode selection signal line for connecting the 1M group of test signals between the memory (2) and the test circuit α1 by switching the selectors (9a) and (9b) during testing, αψ is the test circuit α1) The error detection signal line that indicates the presence or absence of piece movement, 08 is the memory (2).
This is one of the output signal lines for outputting the output signal of the memory (2) normally according to the mode selection signal, and for outputting the error detection signal to the outside during testing.

In this embodiment, the number of additional signal terminals is minimal, with only one input terminal for the activation signal line.

FIG. 5 is a configuration diagram showing the internal configuration of the test M path.

In Figure 5, αQ is an oscillator that generates the operating clock for the test circuit, and ◇γ1 is the memory (2) in Figure 4 during testing.
1. A timing generation circuit that generates test timing and control clock for 1.a~ is an address generation circuit that generates an address signal pattern. α mark is a data generation circuit that generates a write data signal pattern and a data signal pattern for comparison. (A) 1 is a data comparison circuit that compares the data read from the memory (2) in FIG. 4 with an expected value to determine whether the operation is successful, and Qη is a control circuit that controls the above circuit operation.

Since the test circuit αη has a built-in oscillator α0, there is no need to provide a clock. The control circuit Q1) starts the test by a start signal applied through the start signal line. First, a selection signal in the test mode is sent to the selector (9a) in FIG. 4 through the mode selection signal line o4.

(9b), memory (2) and test circuit α in Figure 4]
). Next, the test circuit α→ generates test patterns such as addresses, data, and clock signals for testing the memory (2, 1) in Figure 4, and examines the response from the memory (2) in Figure 4. If a malfunction occurs, this will be notified through the error extraction signal hO threat.When a series of tests is completed, follow the mode selection signal line (11) and send the mode selection signal in the operating mode to the selector (in Figure 4). 9a) and (9b), disconnect the test circuit,
Return to normal memory operating state. The mode selection signal is a signal that identifies whether it is under test or during normal operation.

In the above embodiment, the memory (2) and the test circuit are configured on the same semiconductor substrate in FIG. 4, but as shown in FIG. It goes without saying that it may be constructed on the basis of the basic board. As shown in FIG. 6, the minimum additional terminal required for testing is one terminal connected to the starting signal α. In this embodiment, even if the memory (2) cannot be accessed directly from the outside, it is possible to perform a test on the memory (2j) to ensure its operation. It is unclear whether the problem is a failure or a failure in the logic circuit.According to this embodiment, only the memory can be tested, so it is possible to determine whether the memory part is failure or the logic circuit is malfunctioning. Therefore, it is possible to shorten the repair time in the event of a failure, and
By having a configuration with dual memory, it is also possible to switch to a spare memory in the event of a failure.

Although the configuration example shown in FIG. 5 is shown as the test circuit of the embodiment, it can be implemented using an oscillator, a counter, and a flip-flop, or it can be implemented by microprogram control.

In addition, although the random access read/write memory was described in the embodiment, the same effect can be obtained even in read-only memory by incorporating a circuit for testing data parity. Effects] As described above, according to the present invention, a memory test circuit including an oscillator and a timing generation circuit is configured together with a memory on the same semiconductor substrate, so that unnecessary input/output coding terminals for testing are not added. This has the effect of making it possible to easily perform an effective actual operation test of the memory without having to do so.

Furthermore, since the test is performed near the memory in the semiconductor substrate, there is less delay time due to the test signal path with the outside, and efficient testing with a high failure detection rate is possible at a higher operating frequency.

Since the test timing and test pattern itself can be integrated into the semiconductor substrate according to the characteristics of the memory, it is possible to optimize the test.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram showing the method for testing the four Meshichi Riyo bodies;
FIG. 2 is an explanatory diagram showing a method for testing a device with embedded memory, FIG. 3 is a block diagram showing a test signal path provided in the case of FIG. 2, and FIG. 4 is an implementation of a storage device according to the present invention. FIG. 5 is a block diagram showing the internal structure of the test circuit in FIG. 4, and FIG. 6 is a block diagram showing another embodiment of the present invention. (1)...Memory testing device, (2)...Memory, (
3)...Memory device, (4...Input Bakugo group, (
5]...Output signal line group, (6)...Logic circuit, (7
)...m group of connection signals from the logic circuit to the memory, (8)
... Connection signal line group from memory to logic circuit, (9a)
...Selector, (9b)...Selector, (IQ...
・Switching signal line, αη...Test circuit, α...Start signal line, 0:j...Mode selection signal line, α4...
Error detection signal line, (2)...output signal line, a-ko...
・Oscillator, α...timing generation circuit, 081...
・Address generation circuit, α9...Data generation circuit, Kan・
...Data comparison circuit, Q-control circuit...control circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Haku Kuzuno - Figure 1 -+--"

Claims (1)

[Claims] It is characterized by a memory circuit that stores information, a test circuit that tests this memory circuit, and a selection circuit that connects or separates the memory circuit and the test circuit from each other on one semiconductor substrate. Storage device.