JP2007179731A - Merged memory and logic integrated semiconductor device, and merged memory test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a merged memory and logic integrated semiconductor device provided with first and second memories, pads, logic, and a test control circuit. <P>SOLUTION: A memory data signal which is input to first and second memories and output from the first and the second memories is applied to a plurality of pads. The logic controls the first and the second memories. The merged memory test control circuit transmits the merged memory control signals and the memory data signals to the first and second memories when the first and second memories are tested, and transmits the control signals and the memory data signals to logic block during normal operation. Thereby, the internal merged memory can be tested without increasing a cost. Also a merged memory test time is shortened largely independently of the number of memories. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory logic composite semiconductor device, and more particularly to a memory test circuit for testing a memory of a memory logic composite semiconductor device including a plurality of memories.

Memory logic composite semiconductor device is a lightweight system that uses semiconductor devices.
In order to achieve miniaturization, high performance, and low power, a semiconductor device in which a memory such as a DRAM or SRAM and a logic for controlling the memory are mounted on one chip.

  The memory provided in the semiconductor memory device is tested by connecting a test system to a pad of the semiconductor memory device. However, the memory mounted on the memory logic composite semiconductor device cannot be tested directly from the pad. This is because the memory mounted on the memory logic composite semiconductor device is connected to the pad via the logic mounted on the memory logic composite semiconductor device. Therefore, in order to test the memory mounted on the memory logic composite semiconductor device, another pad is required. However, as the number of pads increases, the memory logic composite semiconductor device becomes larger and the cost increases.

  A technical problem of the present invention is to provide a memory test circuit of a memory logic composite semiconductor device capable of testing a built-in memory using, for example, a pad required for normal operation.

  Another technical object of the present invention is to provide a memory test method for reducing the memory test time of a memory logic composite semiconductor device having a large number of memories.

  In order to achieve the technical problem, a memory logic composite semiconductor device according to the present invention includes a plurality of memories, a plurality of pads for inputting memory control signals for controlling the plurality of memories, and the plurality of pads. Another pad to which a memory data signal that is input to or output from the plurality of memories is applied, logic that controls the plurality of memories, the pads and the other pads, and When the plurality of memories are tested in response to a test control signal, the memory control signal and the memory data signal are transmitted to the plurality of memories. And a test control circuit for transmitting the memory control signal and the memory data signal to the logic when operating normally.

  The memory logic composite semiconductor device according to the present invention includes a first and second memory, a pad to which a memory control signal for controlling the first and second memories is input, and the first and second memories. Other pads to which a memory data signal is input or output from the first and second memories are applied, logic for controlling the first and second memories, the pads and the other pads, and the When the first and second memories are tested, the memory control signal and the memory data signal are transmitted to the first and second memories when connected to the logic and the first and second memories. A test control circuit for transmitting the memory control signal and the memory data signal to the logic.

  The memory logic composite semiconductor device according to the present invention is a memory logic composite semiconductor device having a logic and a memory, and includes a plurality of devices to which at least one clock signal and at least one test enable signal are applied from the outside. Testing the function of the memory in response to the pad, a number of other pads, at least two memories for storing data, the clock signal and the test enable signal, And at least one built-in self-test unit that outputs to the pads.

  The memory logic composite semiconductor device according to the present invention is a memory logic composite semiconductor device having a logic and a memory. The first and second pads to which the first clock signal and the second clock signal are applied from the outside are provided. The third and fourth pads to which the first test enable signal and the second test enable signal are applied from the outside, the fifth and sixth pads, the first and second memories for storing data, and The first memory is connected to the first pad and the third pad, and the function of the first memory is tested in response to the first clock signal and the first test enable signal. A first built-in self-test unit that outputs to a pad, and is coupled to the second memory, the second pad, and the fourth pad; in response to the second clock signal and the second test enable signal; A second built-in self-test unit that tests the function of the second memory and outputs the result to the sixth pad.

  The memory logic composite semiconductor device according to the present invention includes a first pad to which a clock signal is applied from the outside, a first test enable signal, and a second from the outside in a memory logic composite semiconductor device having a logic and a memory. Second and third pads to which a test enable signal is applied, fourth and fifth pads, first and second memories for storing data, the first memory, the first pad, and the second pad A first built-in self-test unit connected to a pad, testing a function of the first memory in response to the clock signal and the first test enable signal, and outputting the result to the fourth pad; 2 is connected to the first pad and the third pad, and tests the function of the second memory in response to the clock signal and the second test enable signal. ; And a second built-in self test unit to be output to the serial fifth pad.

  The memory logic composite semiconductor device according to the present invention is a memory logic composite semiconductor device having a logic and a memory, wherein the first pad for applying a clock signal from the outside, the first test enable signal and the second test from the outside are provided. The second and third pads to which the enable signal is applied, the fourth and fifth pads, the first and second memories for storing data, the first memory, and the first to third pads, respectively. Connected to test the functions of the first memory and the second memory simultaneously or separately in response to the clock signal, the first test enable signal, and the second test enable signal, and the results are respectively A built-in self-test unit for outputting to the fourth pad and the fifth pad;

  In order to achieve the other technical problem, a memory test method according to the present invention provides a memory test method for a memory logic composite semiconductor device having a logic, a memory, and a built-in self test unit. Applying a clock signal and a test enable signal for activating the built-in self-test unit; generating a control signal for testing the function of the memory from the built-in self-test unit; and outputting an output data signal from the memory And generating a test result signal indicating a test result of the memory from the built-in self-test unit.

  According to another aspect of the present invention, there is provided a memory test method for a memory logic composite semiconductor device having a built-in self-test unit connected to the outside and a plurality of memories, wherein the built-in self-test unit includes the plurality of memories. A data writing step for writing data; and a data reading step for reading data stored in the plurality of memories by the built-in self-test unit.

  According to the present invention, for example, the internal memory can be tested using the pad required for the normal operation without adding a significant pad, so that the cost can be reduced. In addition, for example, the memory test time is greatly reduced regardless of the number of memories.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

  FIG. 1 is a block diagram of a memory logic composite semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the memory logic composite semiconductor device 5 according to the first embodiment of the present invention includes pads 7, 8, 9, 10, a memory test control circuit 13, a logic 15, a first memory 17 and a first memory 17. Two memories 19 are provided.

  A memory test control circuit 13 is connected to the pads 7, 8, 9, and 10. A logic 15 and first and second memories (for example, DRAMs) 17 and 19 are connected to the memory test control circuit 13. .

  A memory control signal PC for controlling the first and second memories 17 and 19 is applied to the pad 8, and test control signals TESTMD0 and TESTMD1 for controlling the memory test control circuit 13 are applied to the pads 9 and 10, respectively. The memory data signal DQi input / output to / from the first and second memories 17 and 19 is applied to the pad 7. Pads 7 and 8 are pads that already exist for using the logic 15 and the first and second memories 17 and 19, and pads 9 and 10 are additional pads for controlling the memory test control circuit 13 from the outside. It is.

  When testing the functions of the first and second memories 17 and 19 of the memory logic composite semiconductor device 5, a memory tester (not shown) is connected to the pads 7, 8, 9 and 10. The memory tester inputs the memory control signal PC and the memory data signal DQi to the memory test control circuit 13 through the pads 7 and 8, and controls the memory test control circuit 13 by a combination of the test control signals TESTMD0 and TESTMD1.

  When testing the first and second memories 17 and 19, the memory test control circuit 13 applies the memory control signal PC and the memory data signal DQi to the first and second memories 17 and 19. The first and second memories 17 and 19 operate according to the memory control signal PC and the memory data signal DQi, and then transmit the operation results to the memory test control circuit 13. The memory test control circuit 13 transmits the outputs of the first and second memories 17 and 19 to the memory tester through the pads 7 and 8. The memory tester determines the functions of the first and second memories 17 and 19 by analyzing signals transmitted through the pads 7 and 8.

  When the memory logic composite semiconductor device 5 is operated normally instead of testing the first and second memories 17 and 19, the operation of a part of the memory test control circuit 13 is performed by a combination of the test control signals TESTMD0 and TESTMD1. Stop. In this case, when the memory control signal PC and the memory data signal DQi are applied to the pads 7 and 8 from the outside in order for the memory logic composite semiconductor device 5 to operate normally, both signals are input to the logic 15 and the logic 15 The first and second memories 17 and 19 are controlled through the memory test control circuit 13.

  In the above embodiment, the memory logic composite semiconductor device has two memories, but the number of memories may be one or three or more. When a plurality of memories are mounted, the capacity of each memory may be the same or different from each other.

  According to the memory logic composite semiconductor device 5, the built-in first and second memories 17 and 19 can be tested using the existing pads 7 and 8.

  FIG. 2 is a block diagram showing a first configuration example of the memory test control circuit 13 shown in FIG. As shown in FIG. 2, the memory test control circuit 113 according to the first configuration example includes a main control signal generation unit 23, a memory control signal control unit 25, and a memory data control unit 27.

  The main control signal generator 23 has test control signals TESTMD0 and TESTMD1 applied to its input terminals, and output terminals connected to the memory control signal controller 25 and the memory data controller 27. The main control signal generator 23 generates main control signals MEMTEST1, MEMTEST2, and NORMAL in response to the test control signals TESTMD0 and TESTMD1. The main control signal generator 23 operates as shown in Table 1, for example.

As shown in Table 1, if both the test control signals TESTMD0 and TESTMD1 are logic low ('L'), that is, inactive, the main control signal MEMTEST1 becomes active and the first memory (17 in FIG. 1) is tested. If the test control signal TESTMD0 is logic high ('H'), that is, active and the test control signal TESTMD1 is logic low ('L'), the main control signal MEMTEST2 becomes active and the second memory (FIG. 1 19) is tested.

  If the test control signal TESTMD0 is logic low ('L') and the test control signal TESTMD1 is logic high ('H'), the signal NORMAL becomes active and the logic (15 in Fig. 1) is normal. Operate. Furthermore, if the test control signals TESTMD0 and TESTMD1 are both logic low ('L'), the current state is maintained.

  The memory control signal control unit 25 receives the memory control signal PC applied through the pad 8 and is controlled by the main control signals MEMTEST1, MEMTEST2, and NORMAL, and the memory control signal PC is sent to the first and second memories (FIG. 1 to 17 and 19) or logic (15 in FIG. 1). Examples of the memory control signal PC include a row address strobe signal (RASB), a column address strobe signal (CASB), a write enable signal (WEB), an output enable signal (OEB), and an address signal (Ai).

  The memory data control unit 27 receives the memory data signal DQi applied via the pad 7 and is controlled by the main control signals MEMTEST1, MEMTEST2, and NORMAL, and receives the memory data signal DQi input from the first and first. Memory data transmitted to two memories (17 and 19 in FIG. 1) or logic (15 in FIG. 1) and output from the first and second memories (17 and 19 in FIG. 1) or logic (15 in FIG. 1) Signal DQi is transmitted to pad 7.

  As described above, the memory test control circuit 113 according to the first configuration example uses the existing pads (7 and 8 in FIG. 1) and the first and second without using the logic (15 in FIG. 1). The memory (17 and 19 in FIG. 1) can be tested.

  FIG. 3 is a circuit diagram showing a specific configuration example of the memory control signal control unit 25 shown in FIG. As shown in FIG. 3, the memory control signal control unit 25 includes a buffer 31, a logic gate 33, and a memory control unit 35.

  The buffer 31 receives the memory control signal PC and transmits the output to the logic gate 33. The buffer 31 converts the voltage level of the memory control signal PC. Specifically, the buffer 31 converts, for example, a TTL (Transistor Transistor Logic) level voltage into a CMOS (Complementary Metal Oxide Semiconductor) level voltage.

  The logic gate 33 transmits the output of the buffer 31 to the memory control unit 35. The logic gate 33 includes first to third AND gates 33a, 33b, and 33c.

  The first AND gate 33a receives the output of the buffer 31 and the main control signal MEMTEST1, and outputs a logic low level signal if at least one of the output of the buffer 31 and the main control signal MEMTEST1 is logic low. When the output of the main control signal MEMTEST1 is both logic high, a logic high level signal is output.

  The second AND gate 33b receives the output of the buffer 31 and the main control signal NORMAL, and outputs a logic low level signal if at least one of the output of the buffer 31 and the main control signal NORMAL is logic low. If the output of the main control signal NORMAL and the main control signal NORMAL are both logic high, a logic high level signal is output.

  The third AND gate 33c receives the output of the buffer 31 and the main control signal MEMTEST2, and outputs a logic low level signal if at least one of the output of the buffer 31 and the main control signal MEMTEST2 is logic low. When the output of the main control signal MEMTEST2 is both logic high, a logic high level signal is output.

  The memory control unit 35 includes first and second multiplexers 35a and 35b.

  The first multiplexer 35a is a two-input one-output multiplexer. The first multiplexer 35a receives the output of the first AND gate 33a and the output of the logic (15 in FIG. 1) as inputs, and is controlled by the main control signals NORMAL and MEMTEST1 to output the first AND gate 33a and the logic (in FIG. 1). 15) is selectively transmitted to the first memory (17 in FIG. 1). That is, if the main control signal NORMAL is active, the first multiplexer 35a transmits the signal output from the logic (15 in FIG. 1) to the first memory (17 in FIG. 1), and the main control signal MEMTEST1 is active. If there is, the signal output from the first AND gate 33a is transmitted to the first memory (17 in FIG. 1).

  The second multiplexer 35b is a two-input one-output multiplexer. The second multiplexer 35b receives the output of the third AND gate 33c and the output of the logic (15 in FIG. 1) as inputs, and is controlled by the main control signals NORMAL and MEMTEST2 to output the logic of the third AND gate 33c and the logic (in FIG. 1). 15) is transmitted to the second memory (19 in FIG. 1). That is, if the main control signal NORMAL is active, the second multiplexer 35b transmits the signal output from the logic (15 in FIG. 1) to the second memory (19 in FIG. 1), and the main control signal MEMTEST2 is active. If there is, the signal output from the third AND gate 33c is transmitted to the second memory (19 in FIG. 1).

  FIG. 4 is a circuit diagram showing a specific configuration example of the memory data control unit 27 shown in FIG. As shown in FIG. 4, the memory data control unit 27 includes an input / output buffer 41, a logic gate 43, a memory control unit 45, an output control unit 47, and an output buffer control unit 49.

  The input / output buffer 41 includes an input buffer 41a and an output buffer 41b.

  Input buffer 41a transmits memory data signal DQi to logic gate 43. The input buffer 41a converts the voltage level of the memory data signal DQi. Specifically, the input buffer 41a converts, for example, a TTL level voltage into a CMOS level voltage.

  The output buffer 41b is controlled by the output buffer control unit 49 and transmits the output of the output control unit 47 to the outside. That is, the output buffer 41b is activated when the output of the output buffer control unit 49 is active and transmits the output of the output control unit 47 to the outside, and when the output of the output buffer control unit 49 is inactive. The output of the output control unit 47 is blocked from being deactivated and transmitted to the outside.

  The logic gate 43 receives the output of the input buffer 41a and transmits the output to the memory control unit 45. The logic gate 43 includes first to third AND gates 43a, 43b, and 43c.

  The first AND gate 43a receives the output of the input buffer 41a and the main control signal MEMTEST1, and its output is connected to the memory control unit 45. The first AND gate 43a outputs a logic low signal if at least one of the output of the input buffer 41a and the main control signal MEMTEST1 is logic low, and both the output of the input buffer 41a and the main control signal MEMTEST1 are logic high. If so, a logic high level signal is output.

  The second AND gate 43b receives the output of the input buffer 41a and the main control signal NORMAL, and its output is connected to the logic (15 in FIG. 1). The second AND gate 43b outputs a logic low level signal if at least one of the output of the input buffer 41a and the main control signal NORMAL is logic low, and both the output of the input buffer 41a and the main control signal NORMAL are logic high. If so, a logic high level signal is output.

  The third AND gate 43c receives the output of the input buffer 41a and the main control signal MEMTEST2, and its output is connected to the memory control unit 45. The third AND gate 43c outputs a logic low signal when at least one of the output of the input buffer 41a and the main control signal MEMTEST2 is logic low, and both the output of the input buffer 41a and the main control signal MEMTEST2 are logic high. If so, a logic high level signal is output.

  The memory control unit 45 includes first and second multiplexers 45a and 45b.

  The first multiplexer 45a is a two-input one-output multiplexer. The first multiplexer 45a receives the output of the first AND gate 43a and the output of the logic (15 in FIG. 1) as inputs, and is controlled by the main control signals NORMAL and MEMTEST1, and outputs the first AND gate 43a and the logic (in FIG. 1). 15) is selectively transmitted to the first memory (17 in FIG. 1). That is, if the main control signal NORMAL is active, the first multiplexer 45a transmits the signal output from the logic (15 in FIG. 1) to the first memory (17 in FIG. 1), and the main control signal MEMTEST1 is active. If so, the signal output from the first AND gate 43a is transmitted to the first memory (17 in FIG. 1).

  The second multiplexer 45b is a two-input one-output multiplexer. The second multiplexer 45b receives the output of the third AND gate 43c and the output of the logic (15 in FIG. 1) as inputs, and is controlled by the main control signals NORMAL and MEMTEST2 to output the logic of the third AND gate 43c and the logic (in FIG. 1). 15) is selectively transmitted to the second memory (19 in FIG. 1). That is, if the main control signal NORMAL is active, the second multiplexer 45b transmits the signal output from the logic (15 in FIG. 1) to the second memory (19 in FIG. 1), and the main control signal MEMTEST2 is active. If there is, the signal output from the third AND gate 43c is transmitted to the second memory (19 in FIG. 1).

  The output control unit 47 receives signals output from the logic (15 in FIG. 1) and the first and second memories (17 and 19 in FIG. 1), and transmits the output to the output buffer 41b. As the output control unit 47, a 3-input 1-output multiplexer is used. The output control unit 47 is controlled by main control signals NORMAL, MEMTEST1, and MEMTEST2. That is, the output control unit 47 transmits a signal output from the logic (15 in FIG. 1) to the output buffer 41b if the main control signal NORMAL is active, and the first memory (if the main control signal MEMTEST1 is active) A signal output from 17) in FIG. 1 is transmitted to the output buffer 41b. If the main control signal MEMTEST2 is active, a signal output from the second memory (19 in FIG. 1) is transmitted to the output buffer 41b.

  The output buffer control unit 49 includes first to third OR gates 49a, 49b, 49d, a fourth AND gate 49c, and a NAND gate 49e.

  The first OR gate 49a receives the main control signals MEMTEST1 and MEMTEST2. The first OR gate 49a outputs a logic high level signal when at least one of the main control signals MEMTEST1 and MEMTEST2 is logic high, and outputs a logic low level signal when both the main control signals MEMTEST1 and MEMTEST2 are logic low. To do.

  The second OR gate 49b receives the first output buffer enable signal TRST1 output from the first memory (17 in FIG. 1) and the second output buffer enable signal TRST2 output from the second memory (19 in FIG. 1). And The second OR gate 49b outputs a logic high level signal when at least one of the first and second output buffer enable signals TRST1 and TRST2 is logic high, and the first and second output buffer enable signals TRST1 and TRST2 are both If logic low, a logic low level signal is output.

  The fourth AND gate 49c receives the output of the first OR gate 49a and the output of the second OR gate 49b. The fourth AND gate 49c outputs a logic low level signal if at least one of the output of the first OR gate 49a and the output of the second OR gate 49b is a logic low, and outputs the first OR gate 49a and the second OR gate 49b. If both outputs are logic high, a logic high level signal is output.

  The third OR gate 49d receives the output of the fourth AND gate 49c and the main control signal NORMAL, and outputs a logic high level signal if at least one of the output of the fourth AND gate 49c and the main control signal NORMAL is logic high. If the output of the fourth AND gate 49c and the main control signal NORMAL are both logic low, a logic low level signal is output.

  The NAND gate 49e receives the output of the third OR gate 49d and the power supply voltage VCC, and transmits the output to the control terminal of the output buffer 41b. The NAND gate 49e inverts the output of the third OR gate 49d and transmits it to the control terminal of the output buffer 41b. That is, the NAND gate 49e outputs a logic low level signal if the output of the third OR gate 49d is logic high, and outputs a logic high level signal if the output of the third OR gate 49d is logic low. If the output of the NAND gate 49e is logic low, ie, active, the output buffer 41b is activated. If the output of the NAND gate 49e is logic high, ie, inactive, the output buffer 41b is inactivated.

  FIG. 5 is a block diagram according to a second configuration example of the memory test control circuit 13 shown in FIG. As shown in FIG. 5, the memory test control circuit 213 according to the second configuration example includes the pads 7, 8, 9, 7 ′, the main control signal generation unit 51, the memory control signal control unit 53, and the first memory data control. And a second memory data control unit 57.

  The main control signal generation unit 51 receives the test control signal TESTMD0 applied via the pad 9, and outputs the output to the memory control signal control unit 53, the first memory data control unit 55, and the second memory data control unit 57. introduce. The main control signal generator 51 generates main control signals MEMTEST and NORMAL in response to the test control signal TESTMD0. The main control signal generator 51 operates as shown in Table 2, for example.

As shown in Table 2, if the test control signal TESTMD0 is logic low ('L'), the main control signal MEMTEST becomes active, and the first and second memories (17 and 19 in FIG. 1) are tested. If the test control signal TESTMD0 is logic high ('H'), the main control signal NORMAL becomes active and the logic (15 in FIG. 1) operates normally.

  The memory control signal control unit 53 receives the memory control signal PC applied via the pad 8 and is controlled by the main control signals MEMTEST and NORMAL, and sends the memory control signal PC to the first and second memories (in FIG. 1). 17 and 19) or logic (15 in FIG. 1). The memory control signal PC includes a row address strobe signal (RASB), a column address strobe signal (CASB), a write enable signal (WEB), an output enable signal (OEB), and an address signal (Ai).

  The first memory data control unit 55 receives the memory data signal DQ1i applied via the pad 7, and is controlled by the main control signals MEMTEST and NORMAL, and sends the memory data signal DQ1i to the first memory (17 in FIG. 1). Alternatively, the data is transmitted to the logic (15 in FIG. 1), and the memory data signal DQ1i output from the first memory (17 in FIG. 1) or the logic (15 in FIG. 1) is transmitted from the pad 7 to the outside.

  The second memory data control unit 57 receives the memory data signal DQ2i applied via the pad 7 ′ and is controlled by the main control signals MEMTEST and NORMAL to transfer the memory data signal DQ2i to the second memory (19 in FIG. 1). ) Or logic (15 in FIG. 1), and the memory data signal DQ2i output from the second memory (19 in FIG. 1) or logic (15 in FIG. 1) is transmitted to the pad 7 ′.

  As described above, the memory test control circuit 213 according to the second configuration example uses the existing pads 7, 8, and 7 ′, and the first and second memories (15 in FIG. 1) without using the logic (15 in FIG. 1). 17 and 19) in Fig. 1 can be tested simultaneously.

  FIG. 6 is a circuit diagram showing a configuration example of the memory control signal control unit 53 shown in FIG. As shown in FIG. 6, the memory control signal control unit 53 includes a buffer 61, a logic gate 63, and a memory control unit 65.

  The buffer 61 receives the memory control signal PC and transmits the output to the logic gate 63. The buffer 61 converts the voltage level of the memory control signal PC. Specifically, the buffer 61 converts, for example, a TTL level voltage into a CMOS level voltage.

  The logic gate 63 receives the output of the buffer 61 and transmits the output to the memory control unit 65. The logic gate 63 includes first to third AND gates 63a, 63b, and 63c.

  The first AND gate 63a receives the output of the buffer 61 and the main control signal MEMTEST, and outputs a logic low level signal if at least one of the output of the buffer 61 and the main control signal MEMTEST is logic low. When the output of the main control signal MEMTEST and the main control signal MEMTEST are both logic high, a logic high level signal is output.

  The second AND gate 63b receives the output of the buffer 61 and the main control signal NORMAL and transmits the output to the logic (15 in FIG. 1). The second AND gate 63b outputs a logic low level signal when at least one of the output of the buffer 61 and the main control signal NORMAL is logic low, and both the output of the buffer 61 and the main control signal NORMAL are logic high. For example, a logic high level signal is output.

  The third AND gate 63c receives the output of the buffer 61 and the main control signal MEMTEST. The third AND gate 63c outputs a logic low level signal if any one of the output of the buffer 61 and the main control signal MEMTEST is logic low, and the output of the buffer 61 and the main control signal MEMTEST are all output. If logic high, a logic high level signal is output.

  The memory control unit 65 includes first and second multiplexers 65a and 65b.

  The first multiplexer 65a is a 2-input 1-output multiplexer. The first multiplexer 65a receives the output of the first AND gate 63a and the output of the logic (15 in FIG. 1) as inputs, and is controlled by the main control signals NORMAL and MEMTEST to output the first AND gate 63a and the logic (in FIG. 1). 15) is transmitted to the first memory (17 in FIG. 1). That is, if the main control signal NORMAL is active, the first multiplexer 65a transmits the signal output from the logic (15 in FIG. 1) to the first memory (17 in FIG. 1), and the main control signal MEMTEST is active. If there is, the signal output from the first AND gate 63a is transmitted to the first memory (17 in FIG. 1).

  The second multiplexer 63b is a two-input one-output multiplexer. The second multiplexer 63b receives the output of the third AND gate 63c and the output of the logic (15 in FIG. 1) as inputs, and is controlled by the main control signals NORMAL and MEMTEST to output the logic of the third AND gate 53c and the logic (in FIG. 1). 15) is transmitted to the second memory (19 in FIG. 1). That is, the second multiplexer 65b transmits the signal output from the logic to the second memory (19 in FIG. 1) if the main control signal NORMAL is active, and the third AND gate 63c if the main control signal MEMTEST is active. Is transmitted to the second memory (19 in FIG. 1).

  FIG. 7 is a circuit diagram showing a specific configuration example of the first memory data control unit 55 shown in FIG. As shown in FIG. 7, the first memory data control unit 55 includes a first input / output buffer 71, a first logic gate 73, a first memory control unit 75, a first output control unit 77, and a first output buffer control unit 79. It comprises.

  The first input / output buffer 71 includes a first input buffer 71a and a first output buffer 71b.

  The first input buffer 71a receives the memory data signal DQ1i and transmits the output to the first logic gate 73. The first input buffer 71a converts the voltage level of the memory data signal DQ1i. Specifically, the first input / output buffer 71a converts, for example, a TTL level voltage into a CMOS level voltage.

  The first output buffer 71b is controlled by the first output buffer control unit 79 and transmits the output of the first output control unit 77 to the outside. That is, the first output buffer 71b is activated when the output of the first output buffer control unit 79 is active, and transmits the output of the first output control unit 77 to the outside. When the output is inactive, it is deactivated to block the output of the first output control unit 77 from being transmitted to the outside.

  The first logic gate 73 receives the output of the first input buffer 71a as an input and transmits the output to the first memory control unit 75. The first logic gate 73 includes first and second AND gates 73a and 73b.

  The first AND gate 73a receives the output of the first input buffer 71a and the main control signal MEMTEST, and if at least one of the output of the first input buffer 71a and the main control signal MEMTEST is a logic low signal When both the output of the first input buffer 71a and the main control signal MEMTEST are logic high, a logic high level signal is output.

  The second AND gate 73c receives the output of the first input buffer 71a and the main control signal NORMAL and transmits the output to the logic (15 in FIG. 1). The second AND gate 73c outputs a logic low level signal if at least one of the output of the first input buffer 71a and the main control signal NORMAL is logic low, and the output of the first input buffer 71a and the main control signal NORMAL If both are logic high, a logic high level signal is output.

  The first memory control unit 75 is composed of a 2-input 1-output multiplexer. The first memory control unit 75 receives the output of the first AND gate 73a and the output of the logic (15 in FIG. 1) as inputs, and is controlled by the main control signals NORMAL and MEMTEST to output the first AND gate 73a or logic (see FIG. 1) 15) is transmitted to the first memory (17 in FIG. 1). That is, if the main control signal NORMAL is active, the first memory control unit 75 transmits the signal output from the logic (15 in FIG. 1) to the first memory (17 in FIG. 1), and the main control signal MEMTEST is If active, the signal output from the first AND gate 73a is transmitted to the first memory (17 in FIG. 1).

  The first output control unit 77 is composed of a 2-input 1-output multiplexer. The second output control unit 77 receives signals output from the logic (15 in FIG. 1) and the first memory (17 in FIG. 1), and transmits the output to the first output buffer 71b. The second output control unit 77 is controlled by the main control signals NORMAL and MEMTEST. That is, the first output control unit 77 transmits a signal output from the logic (15 in FIG. 1) to the first output buffer 71b if the main control signal NORMAL is active, and if the main control signal MEMTEST is active. A signal output from the first memory (17 in FIG. 1) is transmitted to the first output buffer 71b.

  The first output buffer control unit 79 includes a third AND gate 79a, a first OR gate 79c, and a first NAND gate 79d.

  The third AND gate 79a receives the main control signal MEMTEST and the first output buffer enable signal TRST1 generated from the first memory (17 in FIG. 1). The third AND gate 79a outputs a logic low level signal if at least one of the main control signal MEMTEST and the first output buffer enable signal TRST1 is logic low, and the main control signal MEMTEST and the first output buffer enable signal TRST1 If both are logic high, a logic high level signal is output.

  The first OR gate 79c receives the output of the third AND gate 79a and the main control signal NORMAL, and outputs a logic high level signal if at least one of the output of the third AND gate 79a and the main control signal NORMAL is logic high. If the output of the third AND gate 79a and the main control signal NORMAL are both logic low, a logic low level signal is output.

  The first NAND gate 79d receives the output of the first OR gate 79c and the power supply voltage VCC and transmits the output to the control terminal of the first output buffer 71b. The first NAND gate 79d inverts the output of the first OR gate and transmits it to the control terminal of the first output buffer 71b. That is, the first NAND gate 79d outputs a logic high level signal if the output of the first OR gate 79c is logic low, and outputs a logic low level signal if the output of the first OR gate 79c is logic high. If the output of the first NAND gate 79d is logic low, ie, active, the first output buffer 71b is activated, and if the output of the NAND gate 79d is logic high, ie, inactive, the first output buffer 71b is deactivated. The

  FIG. 8 is a circuit diagram of the second memory data control unit 57 shown in FIG. As shown in FIG. 8, the second memory data control unit 57 includes a second input / output buffer 81, a second logic gate 83, a second memory control unit 85, a second output control unit 87, and a second output buffer control unit 89. It comprises.

  The second input / output buffer 81 includes a second input buffer 81a and a second output buffer 81b.

  The second input buffer 81a receives the memory data signal DQ2i and transmits the output to the second logic gate 83. The second input buffer 81a converts the voltage level of the memory data signal DQ2i. Specifically, the second input buffer 81a converts, for example, a TTL level voltage into a CMOS level voltage.

  The second output buffer 81b is controlled by the second output buffer control unit 89 and transmits the output of the second output control unit 87 to the outside. That is, the second output buffer 81b is activated when the output of the second output buffer control unit 89 is active, and transmits the output of the second output control unit 87 to the outside. When the output is inactive, it is deactivated to block the output of the second output control unit 87 from being transmitted to the outside.

  The second logic gate 83 receives the output of the second input buffer 81a as an input and transmits the output to the second memory control unit 85. The second logic gate 83 includes fourth and fifth AND gates 83a and 83b.

  The fourth AND gate 83a receives the output of the second input buffer 81a and the main control signal MEMTEST, and if at least one of the output of the second input buffer 81a and the main control signal MEMTEST is a logic low signal If both the output of the second input buffer 81a and the main control signal MEMTEST are logic high, a logic high level signal is output.

  The fifth AND gate 83c receives the output of the second input buffer 81a and the main control signal NORMAL, and transmits the output to the logic (15 in FIG. 1). The fifth AND gate 83c outputs a logic low level signal if at least one of the output of the second input buffer 81a and the main control signal NORMAL is logic low, and the output of the second input buffer 81a and the main control signal NORMAL are If both are logic high, a logic high level signal is output.

  The second memory control unit 85 is composed of a 2-input 1-output multiplexer. The second memory control unit 85 receives the output of the fourth AND gate 83a and the output of the logic (15 in FIG. 1) as inputs, and is controlled by the main control signals NORMAL and MEMTEST to output the fourth AND gate 83a or logic (see FIG. The output of 15 of 1) is transmitted to the second memory (19 in FIG. 1). That is, if the main control signal NORMAL is active, the second memory control unit 85 transmits the signal output from the logic (15 in FIG. 1) to the second memory (19 in FIG. 1), and the main control signal MEMTEST is If active, the signal output from the fourth AND gate 83a is transmitted to the second memory (19 in FIG. 1).

  The second output control unit 87 is composed of a 2-input 1-output multiplexer. The second output control unit 87 receives a signal output from the logic (15 in FIG. 1) and the second memory (19 in FIG. 1) and transmits the output to the second output buffer 81b. The second output control unit 87 is controlled by main control signals NORMAL and MEMTEST. That is, the second output control unit 87 transmits the signal output from the logic (15 in FIG. 1) to the second output buffer 81b if the main control signal NORMAL is active, and if the main control signal MEMTEST is active. A signal output from the second memory (19 in FIG. 1) is transmitted to the second output buffer 81b.

  The second output buffer control unit 89 includes a sixth AND gate 89a, a second OR gate 89c, and a second NAND gate 89d.

  The sixth AND gate 89a receives the main control signal MEMTEST and the output buffer enable signal TRST1 output from the second memory (19 in FIG. 1). The sixth AND gate 89a outputs a logic low signal if at least one of the main control signal MEMTEST and the output buffer enable signal TRST1 is logic low, and both the main control signal MEMTEST and the output buffer enable signal TRST1 are logic high. If so, a logic high level signal is output.

  The second OR gate 89c receives the output of the sixth AND gate 89a and the main control signal NORMAL, and outputs a logic high level signal if at least one of the output of the sixth AND gate 89a and the main control signal NORMAL is logic high, If both the output of the sixth AND gate 89a and the main control signal NORMAL are logic low, a logic low level signal is output.

  The second NAND gate 89d receives the output of the second OR gate 89c and the power supply voltage VCC and transmits the output to the control terminal of the second output buffer 81b. The second NAND gate 89d inverts the output of the second OR gate and transmits it to the control terminal of the second output buffer 81b. That is, the second NAND gate 89d outputs a logic high level signal if the output of the second OR gate 89c is logic low, and outputs a logic low level signal if the output of the second OR gate 89c is logic high. If the output of the second NAND gate 89d is logic low, ie, active, the second output buffer 81b is activated, and if the output of the NAND gate 89d is logic high, ie, inactive, the second output buffer 81b is deactivated. The

  FIG. 9 is a drawing showing a memory logic composite semiconductor device according to the second embodiment of the present invention. As shown in FIG. 9, the memory logic composite semiconductor device 107 according to the second embodiment of the present invention includes first to sixth pads 111, 112, 113, 114, 115, 116, first and second built-ins. Self-test units 121 and 123, first and second memories 125 and 127, and logic 129 are provided.

  A signal is input from the outside into the memory logic composite semiconductor device 107 through the first to fourth pads 111 to 114, and a signal is output from the memory logic composite semiconductor device 107 to the outside through the fifth and sixth pads 115 and 116.

  Specifically, the first and second clock signals Clock_A and Clock_B are input from the outside into the memory logic composite semiconductor device 107 through the first and second pads 111 and 112, respectively, and the third and fourth pads 113 and 114 are input. Then, the first and second test enable signals Enable_A and Enable_B are inputted into the memory logic composite semiconductor device 107 from outside. Further, first and second test result signals Error_A and Error_B are output from the memory logic composite semiconductor device 107 to the outside through the fifth and sixth pads 115 and 116, respectively.

  The first built-in self-test unit 121 receives the first clock signal Clock_A and the first test enable signal Enable_A, and receives the first control signal 131 such as a row address strobe signal (RASB), a column address enable signal (CASB), and an address. A signal (Addr), a write enable signal (WEB), and an input data signal (Datain) are generated and applied to the first memory 125. The first built-in self-test unit 121 receives the first output data signal Dataout_A from the first memory 125 and outputs the first test result signal Error_A to the fifth pad 115.

  The second built-in self-test unit 123 receives the second clock signal Clock_B and the second test enable signal Enable_B, and receives a second control signal 133 such as a row address strobe signal (RASB), a column address enable signal (CASB), and an address signal. (Addr), a write enable signal (WEB), and an input data signal (Datain) are generated and applied to the second memory 127. Then, the second built-in self test unit 123 receives the second output data signal Dataout_B from the second memory 127 and outputs the second test result signal Error_B to the sixth pad 116.

  The first and second memories 125 and 127 are data storage units, and input terminals of the first and second built-in self-test units 121 and 123 are connected to the first and second built-in self-test units, respectively. 121 and 123 are connected to their output ends. The first memory 125 generates a first output data signal Dataout_A in response to the first control signal 131, and the second memory 127 generates a second output data signal Dataout_B in response to the second control signal 133.

  The logic 129 controls the first and second memories 125 and 127.

FIG. 12 is a timing diagram of signals for testing the memory mounted on the memory logic composite semiconductor device according to the second to fourth embodiments of the present invention. As shown in FIG. 12, after the first clock signal Clock_A or the second clock signal Clock_B and the first test enable signal Enable_A or the second test enable signal Enable_B are generated, the first or second control signal (for example, RASB , CASB, Addr, WEB, Data_in) 131 or 133 is generated. Thereafter, after a predetermined time T1 has elapsed, the first or second output data signal dataout_A or Dataout_B is generated. Then, after a predetermined time T2 further elapses, the first or second test result signal Testout_A or Testout_B is generated.

  The operation of the memory logic composite semiconductor device 107 according to the second embodiment of the present invention shown in FIG. 9 will be described with reference to FIG. Here, since the operation of testing the first memory 125 through the first built-in self-test unit 121 and the operation of testing the second memory 127 through the second built-in self-test unit 123 are the same, the first built-in self-test unit 121 Only the operation of testing the first memory 125 will be described.

  When the first test enable signal Enable_A is enabled, that is, when it becomes logic high, the first built-in self-test unit 121 is activated. When the first clock signal Clock_A is enabled to logic high in this state, the first built-in self-test unit 121 activates the first control signal 31. Thus, the first memory 125 generates the first output data signal Dataout_A after a predetermined time (T1 in FIG. 12) has elapsed in response to the first control signal 131, and the first built-in self-test unit 121. Apply to. This predetermined time (T1 in FIG. 12) is a time required for the first memory 125 to be activated simultaneously with the input of the first control signal 131 and to output the result as the first output data signal Dataout_A. is there.

  The first built-in self-test unit 121 analyzes the first output data signal Dataout_A, outputs the result as the first test result signal Error_A, and transmits it to the fifth pad 115. The time required for the first built-in self-test unit 121 to analyze the first output data Dataout_A and output the first test result signal Error_A is T2 (FIG. 12). Whether or not the function of the first memory 125 is normal can be determined based on the first test result signal Error_A.

  As the number of memories mounted on the semiconductor device 107 shown in FIG. 9 increases, the number of built-in self-test units, clock signals, and test enable signals increases with the increase.

  When the first and second test enable signals Enable_A and Enable_B are simultaneously enabled, the first and second memories 125 and 127 are tested simultaneously. Accordingly, the time required to test the first and second memories 125 and 127 is the same as the time required to test one memory, so that the test time can be shortened. Further, the first to sixth pads 111 to 116 are not provided separately, but are shared with pads used in normal operation, whereby the number of pads can be reduced and the cost can be reduced.

  FIG. 10 is a diagram showing a memory logic composite semiconductor device 207 according to the third embodiment of the present invention. As shown in FIG. 10, the memory logic composite semiconductor device 207 according to the third embodiment of the present invention includes first to fifth pads 211, 213 to 216, first and second built-in self-test units 221 and 223. , First and second memories 225 and 227, and logic 229.

  A signal is input from the outside into the memory logic composite semiconductor device 207 through the first to third pads 211 and 213 to 214, and a signal is output from the memory logic composite semiconductor device 207 to the outside through the fourth and fifth pads 215 and 216. Is output.

  Specifically, a clock signal Clock is input from the outside into the memory logic composite semiconductor device 207 through the first pad 211, and the second and third pads 213 and 214 respectively input the clock signal Clock from the outside into the memory logic composite semiconductor device 207. The first and second test enable signals Enable_A and Enable_B are input. Further, the first and second test result signals Error_A and Error_B are output from the memory logic composite semiconductor device 207 to the outside through the fourth and fifth pads 215 and 216, respectively.

  The first built-in self-test unit 221 receives the clock signal Clock and the first test enable signal Enable_A, and receives a first control signal 231 such as a row address strobe signal (RASB), a column address enable signal (CASB), an address signal ( Addr), a write enable signal (WEB), and an input data signal (Datain) are generated and applied to the first memory 225. The first built-in self-test unit 221 receives the first output data signal Dataout_A from the first memory 225 and outputs the first test result signal Error_A to the fourth pad 215.

  The second built-in self-test unit 223 receives the clock signal Clock and the second test enable signal Enable_B, and receives a second control signal 233, for example, a row address strobe signal (RASB), a column address enable signal (CASB), an address signal ( Addr), a write enable signal (WEB) and an input data signal (Datain) are generated and applied to the second memory 227. The second output data signal Dataout_B is received from the second memory 227 and the second test result signal Error_B is output to the fifth pad 216.

  The first and second memories 225 and 227 are data storage units, and input terminals of the first and second built-in self test units 221 and 223 are connected to the first and second built-in self test units, respectively. The output ends are connected to 221 and 223. The first memory 225 generates a first output data signal Dataout_A in response to the first control signal 231 and the second memory 227 generates a second output data signal Dataout_B in response to the second control signal 233.

  The logic 229 controls the first and second memories 225 and 227.

  The operation of the memory logic composite semiconductor device 207 according to the third embodiment of the present invention shown in FIG. 10 will be described with reference to FIG. In the memory logic composite semiconductor device 207 shown in FIG. 10, the operation of testing the first memory 225 through the first built-in self-test unit 221 and the operation of testing the second memory 227 through the second built-in self-test unit 223 are the same. Therefore, only the operation for testing the first memory 225 through the first built-in self-test unit 221 will be described.

  When the first test enable signal Enable_A is enabled, that is, when it becomes logic high, the first built-in self-test unit 221 is activated. In this state, when the clock signal Clock is enabled to logic high, the first built-in self-test unit 221 activates the first control signal 231. As a result, the first memory 225 generates the first output data signal Dataout_A to the first built-in self-test unit 221 after a predetermined time (T1 in FIG. 12) has elapsed in response to the first control signal 231. Apply. This predetermined time (T1 in FIG. 12) is a time required for the first memory 225 to operate simultaneously with the input of the first control signal 231 and to output the result as the first output data signal Dataout_A. is there. The first built-in self-test unit 221 compares and analyzes the first output data signal Dataout_A, outputs the result as the first test result signal Error_A, and transmits the result to the fourth pad 215. The time required from when the first output signal Dataout_A is generated to when the first test result signal Error_A is output is T2 (FIG. 12). Whether or not the function of the first memory 225 is normal can be determined based on the first test result signal Error_A.

  As the number of memories mounted on the semiconductor device 207 shown in FIG. 10 increases, the number of built-in self-test units and test enable signals increases with the increase. However, since the clock signal is shared for each memory, it does not depend on the number of memories.

  When the first and second test enable signals Enable_A and Enable_B are simultaneously enabled, the first and second memories 225 and 227 are tested simultaneously. Accordingly, the time required to test the first and second memories 225 and 227 is the same as the time required to test one memory when the first and second test enable signals Enable_A and Enable_B are simultaneously enabled. Therefore, the test time can be shortened. In addition, the first to fifth pads 211 and 213 to 216 are not provided separately and are shared with pads used in normal operation, whereby the number of pads can be reduced and the cost can be reduced.

  FIG. 11 is a diagram showing a memory logic composite semiconductor device 307 according to the fourth embodiment of the present invention. As shown in FIG. 11, the memory logic composite semiconductor device 307 according to the fourth embodiment of the present invention includes first to fifth pads 311 and 313 to 316, one built-in self-test unit 321, and first memory 325. , A second memory 327, and logic 329.

  A signal is input from the outside into the memory logic composite semiconductor device 307 through the first to third pads 311, 313, 314, and a signal is output from the memory logic composite semiconductor device 307 to the outside through the fourth and fifth pads 315 and 316. The

  Specifically, the clock signal Clock is input from the outside into the memory logic composite semiconductor device 307 through the first pad 311, and the first and third pads 313 and 314 from the outside enter the memory logic composite semiconductor device 307 from the outside. The second test enable signals Enable_A and Enable_B are input. In addition, first and second test result signals Error_A and Error_B are output from the memory logic composite semiconductor device 307 to the outside through the fourth and fifth pads 315 and 316, respectively.

  The built-in self-test unit 321 receives the clock signal Clock and the first and second test enable signals Enable_A and Enable_B, and inputs the first and second control signals 331 and 333, for example, the row address strobe signal (RASB), the column address enable. A signal (CASB), an address signal (Addr), a write enable signal (WEB), and an input data signal (Datain) are generated and applied to the first and second memories 325 and 327, respectively. The built-in self-test unit 321 receives the first and second output data signals Dataout_A and Dataout_B from the first and second memories 325 and 327 and receives the first and second tests on the fourth and fifth pads 315 and 316, respectively. Outputs result signals Error_A and Error_B.

  The first control signal 331 and the second control signal 333 can be made common.

  The first and second memories 325 and 327 are data storage units, and their input terminals are connected to the built-in self-test unit 321 and their output terminals are connected to the built-in self-test unit 321. The first memory 325 generates a first output data signal Dataout_A in response to the first control signal 331, and the second memory 327 generates a second output data signal Dataout_B in response to the second control signal 333.

  The logic 329 controls the first and second memories 325 and 327.

  The operation of the memory logic composite semiconductor device 307 according to the fourth embodiment of the present invention shown in FIG. 11 will be described with reference to FIG.

  When the first test enable signal Enable_A is enabled, that is, when it becomes logic high, the built-in self-test unit 321 is activated. In this state, when the clock signal Clock is enabled to logic high, the built-in self-test unit 321 activates the first control signal 331. Thereby, the first memory 325 generates the first output data signal Dataout_A and applies it to the built-in self-test unit 321 after a predetermined time (T1 in FIG. 12) has elapsed in response to the first control signal 331. This predetermined time (T1 in FIG. 12) is a time required for the first memory 325 to be activated and operated simultaneously with the input of the first control signal 331 and to output the result as the first output data signal Dataout_A. is there. The built-in self-test unit 321 analyzes the first output data signal Dataout_A, outputs the result as the first test result signal Error_A, and transmits it to the fourth pad 315. The time required from the generation of the first output data signal Dataout_A to the output of the first test result signal Error_A is T2 (FIG. 12). Whether or not the function of the first memory 325 is normal can be determined based on the first test result signal Error_A.

  The operation of testing the function of the second memory 327 is the same as the operation of testing the first memory 325. Here, the clock signal Clock and the built-in self test unit 321 are shared by the first and second memories 325 and 327. When the first and second test enable signals Enable_A and Enable_B are enabled at the same time, the first and second memories 325 and 327 are tested at the same time. Therefore, the time required to test the first and second memories 325 and 327 Is the same as the test time of one memory, and the test time can be shortened. Further, by sharing the pads used in the normal operation without separately providing the first to fifth pads 311, 313 to 316, the number of pads can be reduced and the cost can be reduced.

  As the number of memories mounted on the semiconductor device shown in FIG. 11 increases, the number of test enable signals increases with the increase. However, the built-in self-test unit and the clock signal are not shared for each memory and do not depend on the number of memories.

  FIG. 13 is a flowchart showing a memory test method in the memory logic composite semiconductor device 307 according to the preferred embodiment of the present invention. As shown in FIG. 13, a method for testing a memory mounted on the memory logic composite semiconductor device 307 includes a first memory activation stage 401, a second memory activation stage 411, a data reading stage 421 from the first memory, Data read stage 431 from the second memory, data write stage 441 to the first memory, data write stage 451 to the second memory, data reread stage 461 from the first memory, data reread from the second memory An output stage 471, a first memory precharge stage 481 and a second memory precharge stage 491 are provided.

  Hereinafter, a test method according to a preferred embodiment of the present invention will be described with reference to FIG. 11 and FIG.

  In the first memory activation stage 401, the built-in self test unit 321 is activated by an externally input signal, and the built-in self test unit 321 activates the first memory 325. In the second memory activation stage 411, the built-in self-test unit 321 activates the second memory 327.

  In the data reading step 421 from the first memory, the built-in self-test unit 321 reads the data stored in the first memory 325. In the data reading step 431 from the second memory, the built-in self-test unit 321 reads the data stored in the second memory 327.

  In the data writing step 441 to the first memory, the built-in self-test unit 321 writes “1” or “0” data to the first memory 325. In the data writing step 451 to the second memory, the built-in self-test unit 321 writes data “1” or “0” in the second memory 327.

  In the data re-reading step 461 from the first memory, the built-in self-test unit 321 reads the data written in the first memory 325. The built-in self-test unit 321 holds reference data read from the first memory 325 when the first memory 325 is in a normal state, and the built-in self-test unit 321 stores data read from the first memory 325. Is compared with the reference data, and if the read data is different from the reference data, an error signal Error_A is generated and transmitted to the outside.

  In the data re-reading step 471 from the second memory, the built-in self-test unit 321 reads the data written in the second memory 327. The built-in self-test unit 321 compares the data read from the second memory 327 with the reference data for the second memory 327, and generates an error signal Error_B if the read data is different from the reference data. Communicate to the outside.

  In the precharge step 481 of the first memory, the first memory 325 is precharged as a preparatory step for writing data into the first memory 325 or reading data stored in the first memory 325.

  In the precharge stage 491 of the second memory, the second memory 327 is precharged as a preparatory stage for writing data into the second memory 327 or reading data stored in the second memory 327.

  As described above, in this test method, the tests of the first and second memories 325 and 327 are executed in an interleaved manner. Assuming that the first and second memories 325 and 327 are 16M synchronous memories, the test cycle of the first and second memories 325 and 327 is expressed by equation (1) when the 14N Y-March algorithm is used. As shown. Here, it is assumed that the data bus transmits 64 bits.

(Test cycle) = (Data format) x (Stage) x 128K
= 2 × 6 × 128K
= 1,572,864 [cycle time] (1)
In order to simultaneously advance each stage for the first and second memories 325 and 327 in an interleaved manner, 11 clocks are required as shown in Table 3.

Therefore, the total test time of the first and second memories 325 and 327 is as shown in equation (2).

(Test time) = 1,572,864 × 11
= 325,301,504 [cycle time] (2)
The test time shown in the equation (2) is about 55 [%] of the test time in the conventional test orientation. That is, the memory test time according to this embodiment is shortened by 45 [%] from the conventional memory test time.

  It goes without saying that the memory test time is also greatly reduced by applying the interleaving method according to this embodiment to the memory logic composite semiconductor device having three or more memories.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the technical idea of the present invention.

1 is a block diagram of a memory logic composite semiconductor device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a first configuration example of a memory test control circuit shown in FIG. FIG. 3 is a circuit diagram of a memory control signal control unit shown in FIG. FIG. 3 is a circuit diagram of a memory data control unit shown in FIG. FIG. 3 is a block diagram showing a second configuration example of the memory test control circuit shown in FIG. FIG. 6 is a circuit diagram of a memory control signal control unit shown in FIG. FIG. 6 is a circuit diagram of a first memory data control unit shown in FIG. FIG. 6 is a circuit diagram of a second memory data control unit shown in FIG. FIG. 4 is a block diagram of a memory logic composite semiconductor device according to a second embodiment of the present invention. FIG. 6 is a block diagram of a memory logic composite semiconductor device according to a third embodiment of the present invention. FIG. 6 is a block diagram of a memory logic composite semiconductor device according to a fourth embodiment of the present invention. 12 is a timing chart of each signal shown in FIGS. 9 to 11. FIG. 3 is a flowchart showing a memory test method for a memory logic composite semiconductor device according to a preferred embodiment of the present invention.

Explanation of symbols

5 Memory logic composite semiconductor device
7,8,9,10 pad
TESTMD0, TESTMD1 Test control signal
PC memory control signal
DQi memory data signal
MEMTEST1, MEMTEST2, NORMAL main control signal
TRST1 First output buffer enable signal
TRST2 Second output buffer enable signal

Claims (15)

In a memory logic composite semiconductor device having a logic and a memory,
A plurality of pads to which at least one clock signal and at least one test enable signal are externally applied;
With many other pads,
At least two memories for storing data;
In response to the clock signal and the test enable signal, at least one built-in self-test unit that tests the function of the memory and outputs the result to the other multiple pads;
A memory logic composite semiconductor device comprising: The memory logic composite semiconductor device according to claim 1, wherein the memory is a DRAM. In a memory logic composite semiconductor device having a logic and a memory,
First and second pads to which a first clock signal and a second clock signal are applied from the outside, respectively,
Third and fourth pads to which the first test enable signal and the second test enable signal are respectively applied from the outside,
Fifth and sixth pads;
First and second memories for storing data;
The first memory is connected to the first pad and the third pad, and the function of the first memory is tested in response to the first clock signal and the first test enable signal. A first built-in self-test unit that outputs to the fifth pad;
In response to the second clock signal and the second test enable signal, the second memory is connected to the second memory, the second pad, and the fourth pad, and the function of the second memory is tested. A second built-in self-test unit that outputs to the sixth pad;
A memory logic composite semiconductor device comprising: The memory logic composite semiconductor device according to claim 3, wherein the memory is a DRAM. In a memory logic composite semiconductor device having a logic and a memory,
A first pad to which a clock signal is applied externally;
Second and third pads to which a first test enable signal and a second test enable signal are respectively applied from the outside;
The fourth and fifth pads;
First and second memories for storing data;
The first memory is connected to the first pad and the second pad, and the function of the first memory is tested in response to the clock signal and the first test enable signal. A first built-in self-test section that outputs to the pad;
The second memory is connected to the first pad and the third pad, and the function of the second memory is tested in response to the clock signal and the second test enable signal, and the result is applied to the fifth pad. A second built-in self-test unit to output,
A memory logic composite semiconductor device comprising: The memory logic composite semiconductor device according to claim 5, wherein the memory is a DRAM. In a memory logic composite semiconductor device having a logic and a memory,
A first pad to which a clock signal is applied externally;
Second and third pads to which a first test enable signal and a second test enable signal are respectively applied from the outside,
The fourth and fifth pads;
First and second memories for storing data;
The first memory and the first to third pads are connected to the first memory and the second memory in response to the clock signal, the first test enable signal, and the second test enable signal. Embedded self-test unit that tests the function of the same or separately, and outputs the result to the fourth pad and the fifth pad, respectively,
A memory logic composite semiconductor device comprising: The memory logic composite semiconductor device according to claim 7, wherein the memory is a DRAM. In a memory test method for a memory logic composite semiconductor device having logic, memory, and a built-in self-test unit
Applying a clock signal and a test enable signal for activating the built-in self-test unit to the built-in self-test unit;
Generating a control signal for testing the function of the memory from the built-in self-test unit;
Generating an output data signal from the memory;
Generating a test result signal indicating a test result of the memory from the built-in self-test unit;
A memory test method for a memory logic composite semiconductor device, comprising: In a memory test method for a memory logic composite semiconductor device having a built-in self-test unit connected to the outside and a plurality of memories,
A data writing step of writing data to the plurality of memories by the built-in self-test unit;
A data reading step of reading data stored in the plurality of memories by the built-in self-test unit;
A memory test method for a memory logic composite semiconductor device. The data writing step includes
Activating the plurality of memories; and
Reading the data stored in the plurality of memories by the built-in self-test unit;
Writing data into the plurality of memories by the built-in self-test unit;
The memory test method for a memory logic composite semiconductor device according to claim 10, comprising: 12. The step of activating the plurality of memories, wherein the built-in self-test unit activates the plurality of memories by activating the built-in self-test unit from the outside. A memory test method for the described memory logic composite semiconductor device. The data reading step includes
Reading the data stored in the memory by the built-in self-test unit;
Precharging the memory;
The memory test method for a memory logic composite semiconductor device according to claim 10, comprising: In the data writing step, the built-in self-test unit
12. The memory test method for a memory logic composite semiconductor device according to claim 11, wherein data is sequentially written into the plurality of memories. In the data reading step, the built-in self-test unit
11. The memory test method for a memory logic composite semiconductor device according to claim 10, wherein data is sequentially read from the plurality of memories.

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