JPS59152512A - Digital data producer - Google Patents

Abstract

PURPOSE:To always produce digital data on the basis of an accurate slicing level by providing a slice level compensating means which works in response to two types of phase difference signals corresponding to the phase difference component between the output data given from a data slicing circuit and the reading clock signal delivered from a phase locked loop circuit. CONSTITUTION:When a slice level exceeds the normal level V1, the phase is varied for the EFM signal delivered from a data slicing circuit 14. The signals are generated at the output terminals Q of D-FF circuits 30 and 32 by the EFM signal. The signals shown in figures (f) and (g) are produced at the output terminals of D-FF circuits 37 and 38 on the basis of the signals shown in figures (d) and (e) and a synchronizing clock signal. Then finally the signals shown in figures (h) and (i) are delivered from output terminals of an OR circuit 42 and an AND circuit 43 respectively. The polarities of these signals are inverted by NOT circuits 44 and 45 and synthesized each other. This synthesized signal corresponds to the variance of the slice level and is supplied to the inverse terminal of a differential circuit 25. Thus the output voltage of an LPF13 is reduced down to a normal slice level.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a CD (optical compact disc), for example.
The present invention relates to a digital data generation device suitable for use in DAD (digital audio disc) playback devices and the like.

[Technical background of the invention]

Recently, in the field of audio equipment, in order to achieve high fidelity playback as much as possible, digital recording and playback methods using PCM (Russ Code Modulation) technology are being adopted. In other words, this is what is called digital audio, and the audio characteristics often depend on the characteristics of the recording medium, making it much better than the conventional analog recording and playback method. This is because it has been established in principle.

In this case, a system that uses a disk as a recording medium is called a DAD system, and optical, electrostatic, and mechanical recording and reproducing methods have been proposed. Regardless of which method is adopted, the playback device that embodies it is still required to be completely satisfactory, including various advanced control functions and performance that are not found in conventional devices. .

In other words, if we take the CD system as an example,
A specified EFM (Eight to Fou) is placed on a transparent resin disk with a diameter of 12 [α] and a thickness of 1.2 [ttan]
rteenModulation) PCM conversion of the audio signal to be reproduced in any form with modulation and interleaving.

The disk is coated with a metal thin film that forms pits (irregularities with different reflectivity) corresponding to the digitized data that has been digitized.
It is driven to rotate at a variable rotational speed of 0 [r r p'l m], and reproduced in a linear tracking method from the inner circumference side to the outer circumference side using an optical pickup containing a semiconductor laser and a photoelectric conversion element. However, the disc has a track pitch of 1.6 [μm] and has a huge amount of information that can be played in stereo for about an hour on one side in a 70 program area (radius 25-58 cran:).
) are recorded in the lead-in area (radius 23 to 25), and their index data etc.
This can be easily seen from the fact that it is included in

By the way, in the above AD playback device, 1
First, the signal obtained from the optical pickup (hereinafter referred to as RF multiplied signal) is processed by a data slicing circuit to separate unnecessary analog components and necessary data components (hereinafter referred to as EFM signal).
This EFM signal-1'! The E
By generating a synchronous clock signal synchronized with the FM signal and matching the phase of the EFM signal with this synchronous clock signal, digital data that can be used for demodulation and reproduction processing is generated.

FIG. 1 shows such a conventional digital data generation device. That is, the level of the RF multiplied signal supplied to the input terminal 11 is compared with R? is led to a data slice circuit 14 consisting of r12 and U low-pass filter 13,
The output voltage of the low-pass filter 13 (which corresponds to the output frequency of the level comparator 12) is used as a slice level to compare the levels, thereby shaping the waveform into a rectangular EFM signal. After passing through the edge detector 15, this EFM signal passes through the phase comparator 16, the low-pass filter 17 and the '! Pressure controlled oscillator (hereinafter referred to as VCO)
The signal is guided to a PLL circuit 19 for regenerating a synchronous clock consisting of 18 circuits. This synchronous clock regeneration PLL circuit 19 compares the phases of the EFM signal and the output signal of VCO1&, generates a voltage corresponding to the phase difference component in the low-pass filter 17, and controls the oscillation frequency of the VC01B. All the phases of the output signals of the VCO 18 are matched with the EFM signal, and all synchronized clock signals for data reading are generated.

The above EFM signal and synchronized clock signal are supplied to the NOT circuit 2θ and the 944179717021 circuit (hereinafter referred to as D
-FF circuit) 21. This data generation circuit 22 generates digital data that can be used for demodulation and reproduction processing by synchronizing the EFM signal with a synchronization clock signal.

Then, this digital data and the synchronized clock signal are sent to the output terminals 2, ? , 24f, respectively, to a demodulation/reproduction system (not shown).

[Problems with background technology]

Incidentally, the digitized data recorded on the disk has been subjected to EFM modulation, as described above. This is because, as is well known, if one period of the synchronized clock signal is one bit, the polarity inversion interval changes from a minimum of 3 bits to a maximum of 11 bits-i. When the DC component (low frequency component) of the digitized data recorded on the disk is extremely small, the data slice circuit 14 integrates the output of the level comparator 12 with the low-pass filter 13 so that the DC component is Therefore, an accurate Sly/(L/ Herte EFM signal) can be generated.

However, if a level fluctuation occurs in the EFM signal due to scratches on the disk or RF multiplied signal noise, and the level fluctuation becomes faster than the time constant of the low-pass filter 13, the output of the low-pass filter 13 If the voltage is inaccurate, it becomes impossible to generate an EFM signal at an accurate slice level, which results in a problem that digital data cannot be generated satisfactorily.

[Purpose of the invention]

The invention No. 9 was made in consideration of the above-mentioned circumstances, and its purpose is to provide an extremely good digital data generation device that can correct fluctuations in the data slice level and always generate data based on accurate slice levels. do.

[Summary of the invention]

That is, the present invention provides a data slicing circuit that controls the output signal level of the low-pass filter based on the output from a level comparator that compares the levels of input data and the output signal of the low-pass filter, and an output signal from the data slicing circuit. It has a phase comparator that compares the phases of the data and the clock signal output from the voltage controlled oscillator and generates a phase difference signal corresponding to the phase difference component. a phase-locked loop circuit that generates a clock signal for reading data by converting the oscillation frequency of the voltage-controlled oscillator; In a digital data generation device comprising a data generation circuit that adjusts the phase of output data from the circuit, phase comparison is performed between the output data from the data slice circuit and the data reading clock signal output from the phase locked loop circuit. and a data slicing level that generates first and second phase difference signals corresponding to the phase difference component and controls the output signal of the low-pass filter of the data slicing circuit based on the first and second phase difference signals. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 2, the same parts as in FIG. 1 are designated by the same symbols, and only the different parts will be described here. First, the low-pass filter 13 consists of a differential circuit 25, a resistor Rlr R2, and a capacitor ClIC2, and corresponds to the difference between the output signal from the level comparator 12 and the output signal from a data slice level correction circuit 26, which will be described later. It outputs a voltage signal. Further, the synchronized clock signal outputted from the clock reproduction PLL circuit 19 and the digital data outputted from the D-FF circuit 21 are supplied to a demodulation/reproduction circuit 27 and subjected to well-known demodulation/reproduction processing.

Here, the data slice level correction circuit 26 compares the phases of the EFM signal output from the data slice circuit 14 and the synchronous clock signal output from the synchronous clock regeneration PLL circuit 19, and calculates the phase difference component. It outputs a pair of corresponding phase difference signals. That is,
The output terminal of the one-novel comparator 12 is connected to a first input terminal of an AND circuit 28 and a first input terminal of an OR circuit 29, respectively, and is connected to a clock input terminal C of a D-FF circuit 30. ing. In addition, the level comparator 12
After passing through the NOT circuit 31, the output terminal is connected to the clock input terminal C of the D-FF circuit 32, and is also connected to the third input terminal of the AND circuit 33 and the third input terminal of the OR circuit 34, respectively. It is connected. Further, each input terminal DVi of the D-FF circuit 30, 32 is connected to a power supply terminal 35 to which a DC voltage of 10 B is applied.

The output terminal Q of the upper WeD-FF circuit 3o is connected to the second input terminal of the AND circuit 28, and the inverting input terminal 1 is connected to one input terminal of the NAND circuit 36. The output terminal Q of the D-FF circuit 32 is open, and the inverted output terminals are connected to the third input terminal of the OR circuit 29 and to the other input terminal of the NAND circuit 36. The output terminal of this NAND circuit 36 is a D-FF
It is connected to each input end of circuits 37 and 38, respectively. Further, the output terminal of the synchronous clock regeneration PLL circuit 19 is connected to the clock input terminal C of the D-FF circuit 38 and also connected to the clock input terminal C of the D-FF circuit 37 via the NOT circuit 39. has been done.

Here, the output terminal Q of the D-FF circuit 37 is connected to the first input terminal of the OR circuit 34 and to one input terminal of the AND circuit 40. The inverting input terminal of the D-FF circuit 37 is connected to the AND circuit 3.
3. And the above D-
The output terminal Q of the FF circuit 38 is connected to the second terminal of the AND circuit 33.
and the second input terminal of the OR circuit 29, and is connected to the other input terminal of the AND circuit 40. In addition, the D-1'F circuit 38
The inverted output terminal Q of is connected to the third input terminal of the AND circuit 28 and the second input terminal of the OR circuit 34, respectively.

The output terminal of the AND circuit 40 is connected to the NOR circuit 41.
is connected to one input end of the

In fact, the demodulation/reproduction circuit 27 is connected to the other input terminal of the NOR circuit 41. And this Noah circuit 4
The output terminals of the D-FF circuits 30, . 32 clear input terminals CL, respectively.

Here, each output terminal of the AND circuit 28 and 33 is connected to both input terminals of the OR circuit 42. Further, each output terminal of the OR circuit 29 and 34 is connected to both input terminals of the AND circuit 43. The output terminals of the OR circuit 42 and the AND circuit 43 are connected via a NOT circuit 44, 45 and resistors R3 and R4, respectively, and the connection point is the differential circuit 25 of the low-gust filter 13. Connected to the inverting input terminal.

The operation of the above configuration will be described below with reference to FIGS. 3 and 4. However, Figures 3 and 4
The diagrams show differences when the data slice level becomes high and low, respectively, and Figures 3 (,) to (i
) and Figures 5(a) to (i) are respectively shown in Figure 2 (
The timing of points a) to (1) is shown.

If a W signal as shown in FIG. 3(a) is supplied to the input terminal 11, and a synchronous clock signal as shown in FIG. 3(b) is generated from the synchronous clock regeneration PLL circuit 19. do. At this time, the voltage signal (data slice level) output from the low-pass filter 13 is
) Suppose that the slice level v1 is higher than the normal slice level v1 shown by the solid line, as shown by the dashed line. Then, the EFM signal output from the data slice circuit 14 has the normal slice level ■1, as shown in FIG.
The phase is changed compared to when it was generated.

Then, by the signal shown in FIG. 3(c), the D-FF
At the output terminal Q of the circuit 3θ, 32, there are shown in FIG.
The signals shown in e) are generated. Also, this third
Based on the signals shown in FIGS. (d) and (e) and the synchronous clock signal, the D-FF circuit 37, , ? At the output terminal of 8, the signals shown in FIGS. 3(f) and 3(g) are generated.

Therefore, the output terminals of the OR circuit 42 and the AND circuit 43 output the signals shown in FIG. 3(h) and (+), respectively.

Here, when the EFM signal shown in FIG. 3(c) becomes H level, the signal shown in FIG. 3(h) is the EFM signal shown in FIG. 3(c) and the signal shown in FIG. 3(b). It has an H level period corresponding to the phase difference component with respect to the synchronous clock signal, and has an H level period corresponding to the phase difference component with respect to the synchronous clock signal.
The signal shown in 1) has an I level period corresponding to a half period of the synchronous clock signal shown in FIG. 3(b). Also, the EF'M signal shown in FIG. 3(c) is L.
level, the signal shown in FIG. 3(1) has an L level period corresponding to the phase difference component between the signal shown in FIG. 3(c) and the signal shown in FIG. 3(b), The signal shown in FIG. 3(h) has an H level period corresponding to a half period of the signal shown in FIG. 3(b) K. In addition, in this case, from the H level period of the signal shown in FIG. 3(h),
The L level period of the signal shown in FIG. 3(i) is longer.

For this reason, the polarity of the signals shown in FIG. 3(h) and (i) is inverted by the knot circuits 44 and 45, and the signals obtained by mutually inverting the polarity and combining the signals correspond to the fluctuations in the slice level.
By supplying this to the inverting input terminal of the differential circuit 25, the output voltage of the loaf 4 filter 13 can be lowered to the normal slice level. Next, assume that the voltage signal (data slice level) output from the low-pass filter 13 has become lower than the normal slice level V] shown by the solid line in FIG. 4(a), as shown by the dashed line. Then, as shown in FIG. 4(c), the phase of the EFM signal output from the data slice circuit 14 is changed compared to when it is generated at the normal slice level 1.

In this case as well, the EFM shown in FIG. 4(c)
When the signal becomes H level, the signal shown in FIG. 4(h) becomes H level corresponding to the phase difference component between the EFM signal shown in FIG. 4(c) and the synchronized clock signal shown in FIG. 4(b). The signal shown in FIG. 4(i) has an L level period corresponding to a half period of the synchronous clock signal shown in FIG. 4(b). Moreover, when the EFM signal shown in FIG. 4(c) becomes L level, the signal shown in FIG. 4(0) is a combination of the signal shown in FIG. 4(c) and the signal shown in FIG. 4(b). It has an L level period corresponding to the phase difference component, and the fourth
The signal shown in FIG. 4(h) has an H level period corresponding to a half period of the signal shown in FIG. 4(b).

Further, in this case, the H level period of the signal shown in FIG. 4(f) is longer than the L level period of the signal shown in FIG. 4(i).

For this reason, the polarity of the signals shown in FIG. 3(h) and (i) is inverted by the knot circuits 44 and 45, respectively, and the resulting signal, which is combined with each other, corresponds to the variation in the slice level.
By supplying this to the inverting input terminal of the differential circuit 25, the output voltage of the low-pass filter 13 can be raised to the normal slice level.

Here, a signal (Fig. 3(f), (g) and Fig. 4(
As a means for obtaining (corresponding to (g)), although approximate, a D-FF circuit 46.f) is used as shown in FIG.
47, AND circuit 48.49 and NOT circuit 50 to 5
2, substantially the same operation can be performed.

In this case, the output terminal 53 is connected to the synchronous clock regeneration circuit 1.
9, the input terminal 54 is supplied with the synchronous a work signal, and the output terminal 55.56 is connected to the signal shown in FIG.
.

Signals corresponding to (g) and FIGS. 4(f) and (g) are obtained, and this is the Rono J? This is to control the filter 13.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, it is possible to provide an extremely good digital data generation device that can correct fluctuations in data slice levels and always generate data based on accurate slice levels.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing a conventional digital data generation device, FIG. 2 is a block circuit configuration diagram showing an embodiment of the digital data generation device according to the present invention, and FIGS. 3 and 4 are the same. A timing diagram for explaining the operation of the embodiment, and FIG. 5 is a block configuration diagram showing a modification of the embodiment. 11...Input terminal, 12...Level comparator, 13.
- Ronos filter, 14... Data slice circuit, 15... Edge detector, 16... Phase comparator, 1
7...Low pass filter, 18...VCO519・
... PLL circuit for synchronous clock regeneration, 20 ... Not circuit, 21 ... D-FF circuit, 22 ... Data generation circuit, 2.9, 24 ... Output terminal, 25 ... Differential Circuit, 26... Data slice level correction circuit, 27
... Demodulation/reproduction circuit, 28... AND circuit, 29...
・OR circuit, 30...D-FF circuit, 31...NOT circuit, 32...D-FF circuit, 33...AND circuit, 34...OR circuit, 35...power terminal, 36・
...NAND circuit, 37.38...D-FF circuit, 39
... knot circuit, 4Q ... and [ol path, 41.
...NOR circuit, 42...OR circuit, 43...AND circuit, 44.45...not circuit, 46°47...
D-FF circuit, 48.49...AND circuit, 50 to 52...NOT circuit, 53...Output terminal, 54...
・Input terminal, 55.56...output terminal. Applicant's representative Patent attorney Takehiko Suzue Figure 3 (i) '', ?4 Figure 1

Claims (1)

[Claims] A data slice circuit that controls the output signal level of the low-pass filter based on the output from a level comparator that compares the levels of input data and the output signal of the low-e pass filter, and output data and voltage from the data slice circuit. It has a phase comparator that compares the phase of the clock signal output from the controlled oscillator and generates a phase difference signal corresponding to the phase difference component, and converts the phase difference signal output from the phase comparator into a voltage signal. a phase-locked loop circuit that generates a clock signal for reading data by controlling the oscillation frequency of the voltage-controlled oscillator; and a phase-locked loop circuit that generates a clock signal for reading data by controlling the oscillation frequency of the voltage-controlled oscillator; In the digital data generation device, the output data of the data slicing circuit and the data reading clock signal outputted from the phase-locked loop circuit are compared in phase and the phase difference is determined. fc first corresponding to the component
and data slice level correction means for generating a second phase difference signal and controlling the output signal of the low-pass filter of the data slice circuit based on the first and second phase difference signals. Digital data generation device.