JPH087468A - Optical disk reproducing device - Google Patents

Abstract

PURPOSE:To properly reproduce a disk even though a reproduced linear speed is greatly deviated from a normal speed as in the case of right after a track search by generating an optimum VCO frequency, which makes the device to follow the change in a reproducing speed, as a data reading clock. CONSTITUTION:The device is provided with a synchronization pattern detecting circuit 16 which detects a synchronization pattern from EFM signals, an F-V converting circuit 17 which converts the period of synchronization pattern detection pulses to a voltage and an adding circuit 15 which adds the voltage obtained by the circuit 17 and the phase difference voltage obtained by a phase comparator 11 and applies the voltage to a VCO circuit 12 as a control voltage. The oscillating frequency of the circuit 12 varies from the condition, in which the oscillation frequency is synchronized with a reproducing speed, to the condition in which the oscillation frequency is increased in proportion with the reproducing speed, i.e., in proportion with the output voltage of the circuit 17. Thus, an optimum data reading clock is generated while following a reproducing speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk reproducing apparatus for reproducing an optical disk such as a CD-ROM.

[0002]

2. Description of the Related Art Compact discs (CDs) and CDs
The reproduction of the optical disc such as the ROM is performed by the CLV method, that is, the constant linear velocity. Therefore, it is necessary to control the rotation speed of the disc so that the reproduction linear velocity falls within the specified range according to the track position to be reproduced. This control is
This is performed by detecting a sync pattern for reproduction synchronization included in the EFM signal and controlling the rotation speed of the disk motor so that the sync pattern appears in a constant cycle.

On the other hand, in such an optical disk reproducing apparatus, a data reading clock is generated from a frequency component of the EFM signal by using a PLL circuit. Figure 10 shows this PL
It is a figure which shows the structure of an L circuit. In the figure, reference numeral 1 is a phase comparator, which is a signal obtained by dividing the EFM signal read from the disc through an optical pickup or the like and the oscillation frequency of the VCO circuit 2 by a 1/2 divider 3 at a ratio of 1/2. And the phase difference signal is output. After the high frequency component is removed from the phase difference signal through the loop filter 4, V
It is applied as a control voltage to the CO circuit 2, and the oscillation frequency of the VCO circuit 2 is controlled by this control voltage. VCO
The oscillating frequency of the circuit 2 is divided by the ½ frequency divider 3 and supplied to the data reading circuit 6 as a data reading clock and also output to the phase comparator 1 as a phase comparison reference signal with the EFM signal. It

The oscillation frequency of the VCO circuit 2 in this PLL circuit takes a value greatly apart from the center value for a prescribed reproduction speed, as shown in FIG. 11, for reasons such as the operating characteristics of the phase comparator 1. I can't. In the figure, the shaded area is the range of the oscillation frequency of the VCO circuit 2. Therefore, the range of the disc reproduction speed at which the disc information can be read is limited to a very narrow range near the prescribed reproduction speed.

Therefore, in order to start the disc reproduction immediately after the track search, it is indispensable to keep the reproduction linear velocity within the specified range by using the disc motor having a short control response time. Therefore, a large and expensive motor control system is required.

[0006]

As described above, in the conventional optical disc reproducing apparatus, since the range of the reproducing speed at which the disc information can be read is limited to the narrow range near the prescribed reproducing speed, the track search is performed. In order to start disc reproduction at a later speed, a powerful disc motor with excellent control response must be used. Therefore, there is a problem that a large and expensive motor control system is required.

The present invention has been made to solve the above problems, and an optical disk capable of reproducing a disc satisfactorily even when the reproduction linear velocity is largely deviated from a prescribed velocity immediately after a track search. The purpose is to provide a playback device.

[0008]

In order to achieve the above-mentioned object, a first aspect of the present invention is to provide a voltage-controlled oscillation means capable of controlling an oscillation frequency based on an applied control voltage, and an EFM signal read from a disk. And a phase comparison means for comparing the phases of the output signal of the voltage controlled oscillation means with each other to generate a voltage corresponding to the phase difference, a synchronization pattern detection means for detecting a synchronization pattern from the EFM signal, and the synchronization pattern. A conversion unit that converts the period of the synchronization pattern detected by the detection unit into a voltage, an output voltage of the phase comparison unit and an output voltage of the conversion unit are added, and added as a control voltage to the voltage controlled oscillation unit. And means.

The second aspect of the present invention is to control the oscillation frequency based on the applied control voltage, the voltage control oscillation means, and the phase of the EFM signal read from the disk and the output signal of the voltage control oscillation means. In comparison, a phase comparison means for generating a voltage according to the phase difference, a synchronization pattern detection means for detecting a synchronization pattern from the EFM signal, and a cycle of the synchronization pattern detected by the synchronization pattern detection means as a voltage. First conversion means for converting, and frequency division means for dividing the oscillation frequency of the voltage controlled oscillation means by a division ratio such that the period matches the synchronization pattern when the oscillation frequency is synchronized with the reproduction speed. Second conversion means for converting the output frequency of the frequency dividing means into a voltage, and a differential amplifier for amplifying the difference between the output voltage of the first conversion means and the output voltage of the second conversion means. When the by adding the output voltage of the output voltage and the differential amplifier means of the phase comparing means, those obtained by including an adding means for adding a control voltage to said voltage controlled oscillation means.

Further, a third aspect of the invention is a voltage-controlled oscillation means capable of controlling the oscillation frequency based on the applied control voltage,
Phase comparison means for comparing the phases of the EFM signal read from the disk and the output signal of the voltage controlled oscillation means, and generating a voltage according to the phase difference, and synchronization for detecting a synchronization pattern from the EFM signal. The pattern detecting means, the first converting means for converting the period of the synchronous pattern detected by the synchronous pattern detecting means into a voltage, and the oscillation frequency of the voltage controlled oscillating means when the oscillation frequency is synchronized with the reproduction speed. Frequency dividing means for dividing at a dividing ratio such that the period matches the synchronization pattern, second converting means for converting the output frequency of the dividing means into a voltage, and output voltage of the first converting means. A differential amplifier for amplifying a difference from the output voltage of the second converter, an output voltage of the phase comparator, an output voltage of the first converter, and an output voltage of the differential amplifier. San, those obtained by including an adding means for adding a control voltage to said voltage controlled oscillation means.

[0011]

The EFM signal read from the optical disk contains the synchronization pattern. This synchronization pattern is generated in a constant cycle in proportion to the reproduction linear velocity. Therefore, the generation period of this synchronization pattern is detected by the synchronization pattern detection means, and the period of this synchronization pattern is converted into a voltage, whereby a voltage proportional to the reproduction linear velocity is obtained.

In the first aspect of the present invention, the voltage corresponding to the cycle of the synchronization pattern and the phase difference voltage output from the phase comparison means are added by the addition means, and the addition result is applied to the voltage controlled oscillation means as the control voltage. Add as. As a result, the oscillation frequency of the voltage controlled oscillator increases from the state of being synchronized with the EFM signal, in proportion to the value obtained by converting the period of the synchronization pattern into voltage, that is, in proportion to the reproduction speed. Therefore,
According to the present invention, an optimum oscillation frequency can be generated as a data reading clock by following the reproduction speed.

According to the second aspect of the invention, the oscillation frequency of the voltage-controlled oscillation means is divided by a division ratio such that the period coincides with the synchronization pattern when the oscillation frequency is synchronized with the reproduction speed. Converts the frequency of the divided signal to voltage. The differential amplifying means amplifies the difference between the value obtained by converting the frequency of the divided signal into a voltage and the value obtained by converting the period of the synchronization pattern into a voltage, and outputs the amplified voltage and the output from the phase comparing means. The phase difference voltage is added by the addition means, and the addition result is added to the voltage controlled oscillation means as a control voltage. Thus, according to the present invention, it is possible to control the oscillation frequency of the voltage control oscillation means so as to correct the deviation between the oscillation frequency of the voltage control oscillation means and the reproduction speed, and follow the change of the reproduction speed to optimize the operation. Various oscillation frequencies can be generated as the data reading clock.

Further, in the third invention, the value obtained by converting the period of the synchronization pattern into a voltage by the adding means, the phase difference voltage output from the phase comparing means, and the output voltage of the differential amplifying means is added to obtain a voltage. Since it is applied as a control voltage to the control oscillating means, the effect of correcting the deviation between the oscillation frequency of the voltage controlled oscillating means and the reproduction speed is added to the effect of making the oscillation frequency of the voltage controlled oscillating means follow the cycle of the synchronization pattern. More accurate control can be realized as compared with the case where either one is controlled.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a P for generating a data reading clock in an optical disk reproducing apparatus according to an embodiment of the present invention.
It is a figure which shows the structure of a LL circuit.

In the figure, 11 is a phase comparator,
EF read from a disc through an optical pickup
The phase difference signal is output by comparing the phases of the M signal and the signal obtained by dividing the oscillation frequency of the VCO circuit 12 by the 1/2 divider 13 at a ratio of 1/2. The phase difference signal is input to the adding circuit 15 after the high frequency component is removed through the loop filter 14. Reference numeral 16 is a sync pattern detection circuit for detecting a sync pattern for reproduction synchronization included in the EFM signal. The sync pattern detection pulse output from the sync pattern detection circuit 16 is input to the FV (frequency-voltage) conversion circuit 17. F-V conversion circuit 1
Reference numeral 7 converts the cycle of the sync pattern detection pulse into a voltage, which is input to the adding circuit 15 through the loop filter 18.

FIG. 2 is a diagram showing the configuration of the FV conversion circuit 17, and FIG. 3 is a diagram for explaining the operation of the FV conversion circuit 17. As shown in FIG. 2, the F-V conversion circuit 17
Is composed of a flip-flop 21 and a counter 22. The sync pattern detection pulse from the sync pattern detection circuit 16 is supplied to the flip-flop 21 as a set signal, and the output of the counter 22 is input as a reset signal. The counter 22 starts counting according to the reference clock from the time when the flip-flop 21 is set, and outputs a reset signal to the flip-flop 21 when the count number reaches a predetermined value. Therefore, the output time of the flip-flop 21 (pulse-on time within one cycle) becomes constant. On the other hand, the output stop time of the flip-flop 21 (pulse off time within one cycle) is the time obtained by subtracting the output time from the pulse input interval. Therefore, the shorter the sync pattern generation period, the shorter the output stop time,
The average voltage per cycle becomes high. That is, F-V
The output voltage of the conversion circuit 17 increases in proportion to the reproduction speed of the disc.

The adder circuit 15 uses the FV conversion circuit 17
And the phase difference voltage input from the phase comparator 11 are added and applied to the VCO circuit 12 as a control voltage.
The oscillation frequency of the VCO circuit 12 is 1 in the 1/2 frequency divider 13.
After being divided by the ratio of / 2, it is supplied to the data reading circuit 19 as a data reading clock and at the same time, the phase comparator 1
Input to 1.

The oscillation frequency of the VCO circuit 12 changes from the state in which the EFM signal is synchronized with the output frequency of the 1/2 frequency divider 13 (1/2 VCO frequency), that is, the state in which the PLL circuit is synchronized with the reproduction speed, to FV. The output voltage of the conversion circuit 17 increases in proportion to the reproduction speed. FIG. 4 shows this VCO circuit 12
It is a figure showing the range of the oscillation frequency. In the figure,
Each hatched portion shows the variation range of the oscillation frequency of the VCO circuit 12 with respect to a specific reproduction speed.
In the PLL circuit of this embodiment, the range of the oscillation frequency indicated by the diagonal lines shifts in the area surrounded by A and B according to the reproduction speed.

Therefore, according to this PLL circuit, it becomes possible to generate an optimum data reading clock by following the reproduction speed, and until the reproduction linear velocity converges on the prescribed speed as immediately after the track search. It is possible to satisfactorily perform the disc reproduction during the period. Therefore, it is possible to realize an optical disc reproducing device that can start disc reproduction immediately after a track search in a short time regardless of the control response time of the disc motor, and it is possible to provide a compact and low-priced device.

Next, another embodiment of the present invention will be described. Figure 5
FIG. 3 is a diagram showing a configuration of a PLL circuit of this embodiment.

In the figure, 41 is a phase comparator,
EF read from a disc through an optical pickup
The phase of the M signal is compared with the phase of the signal obtained by dividing the output of the VCO circuit 42 by the 1/2 divider 43 at a ratio of 1/2, and the phase difference signal is output. The phase difference signal has its high frequency component removed through the loop filter 44, and then added by the adder circuit 45.
Is input to Reference numeral 46 is a sync pattern detection circuit that detects a sync pattern for reproduction synchronization included in the EFM signal. The sync pattern detection pulse output from the sync pattern detection circuit 46 is input to the first FV conversion circuit 47. The first F-V conversion circuit 47 converts the cycle of the sync pattern detection pulse into a voltage, and the differential circuit 4
Enter in 8.

Reference numeral 49 is a 1/588 frequency divider. The 1/588 frequency divider 49 further divides the output frequency of the 1/2 frequency divider 43 by a ratio of 1/588. The output frequency of the 1/588 frequency divider 49 is converted into a voltage by the second F-V conversion circuit 50 and then applied to the differential circuit 48. As shown in FIG. 6, the differential circuit 48 includes the second F-V conversion circuit 5
The difference between the output voltage VVCO of 0 and the output voltage VCYN of the first FV converting circuit 47 is amplified, and the amplified signal is input to the adding circuit 45 through the loop filter 51.

The adder circuit 45 adds the phase difference voltage obtained by the phase comparator 41 and the voltage obtained by the differential circuit 48, and applies the addition result to the VCO circuit 42 as a control voltage. V
The oscillation frequency of the CO circuit 42 is frequency-divided by the 1/2 frequency divider 43 and then supplied to the data reading circuit 52 as a data reading clock, and at the same time, the phase comparators 41 and 1/5.
It is input to each of the 88 frequency dividers 49.

FIG. 7 is a diagram showing an input example to the differential circuit 48. In the figure (A), when the reproduction speed is higher than the 1/2 VCO frequency which is the output frequency of the 1/2 frequency divider 43,
(B) shows the input state of each voltage VVCO, VCYN when the reproduction speed is synchronized with the 1/2 VCO frequency, and (C) shows the input state of each voltage VVCO, VCYN when the reproduction speed is low with respect to the 1/2 VCO frequency. There is.

As shown in (B), when the reproduction speed is synchronized with the 1/2 VCO frequency, the cycle TVCO of the output signal of the 1/588 frequency divider 49 and the cycle TCYN of the sync pattern generation are the same. And each F-V conversion circuit 47, 50
The average values of the output voltages VSYN and VVCO of 1 are the same. In this case, the output of the differential circuit 48 becomes the reference voltage, and the oscillation frequency of the VCO circuit 42 does not change.

As shown in (A), when the reproduction speed is higher than the 1/2 VCO frequency, the sync pattern generation period T is longer than the output signal period TVCO of the 1/588 frequency divider 49.
CYN becomes shorter, and the average value of the output voltage VSYN of the first F-V conversion circuit 47 per cycle becomes higher than the average value of the output voltage VVCO of the second F-V conversion circuit 50 per cycle. . As a result, the output of the differential circuit 48 becomes higher than the reference voltage, and the oscillation frequency of the VCO circuit 42 becomes high.

As shown in (C), when the reproduction speed is lower than the 1/2 VCO frequency, that is, the 1/588 frequency divider 4
When the generation cycle TCYN of the sync pattern is longer than the cycle TVCO of the output signal of No. 9, the average value of the output voltage VSYN of the first F-V conversion circuit 47 per one cycle of the second F-V conversion circuit 50. The output voltage VVCO becomes lower than the average value per cycle. As a result, the output of the differential circuit 49 becomes smaller than the reference voltage, and the oscillation frequency of the VCO circuit 42 becomes low.

The oscillation frequency of the VCO circuit 42 increases in proportion to the output voltage of the differential circuit 48 from the state where the EFM signal and the 1/2 VCO frequency are synchronized, that is, the state where the PLL circuit is synchronized with the reproduction speed. Therefore, according to this PLL circuit, it becomes possible to control the output frequency of the VCO circuit 42 so as to correct the deviation between the 1/2 VCO frequency and the reproduction speed. Therefore, even with this PLL circuit, it becomes possible to generate the optimum data reading clock by following the reproduction speed, as in the previous embodiment, and the reproduction linear speed is the specified speed as immediately after the track search. It is possible to satisfactorily perform the disc reproduction until it converges on.

Next, another embodiment of the present invention will be described. FIG. 8 is a diagram showing the configuration of the PLL circuit of this embodiment.

In the figure, 71 is a phase comparator,
EF read from a disc through an optical pickup
The phase difference signal is output by comparing the phases of the M signal and the signal obtained by dividing the oscillation frequency of the VCO circuit 72 by the 1/2 divider 73 at the ratio of 1/2. The phase difference signal is input to the adder circuit 75 after the high frequency component is removed through the loop filter 74. A sync pattern detection circuit 76 detects a sync pattern for reproduction synchronization included in the EFM signal. The sync pattern detection pulse output from the sync pattern detection circuit 76 is input to the first FV conversion circuit 77. First F-V conversion circuit 77
Converts the cycle of the sync pattern detection pulse into a voltage and inputs it to the differential circuit 78, and inputs it to the addition circuit 75 through the loop filter 79.

Further, 80 is a 1/588 frequency divider. The 1/588 frequency divider 80 further divides the output frequency of the 1/2 frequency divider 73 by a ratio of 1/588. The output frequency of the 1/588 frequency divider 80 is converted into a voltage by the second FV conversion circuit 81, and then added to the differential circuit 78. The differential circuit 78 outputs the output voltage VVCO of the second F-V conversion circuit 80.
And the output voltage VCYN of the first F-V conversion circuit 77 are amplified and input to the addition circuit 75 through the loop filter 82.

The adder circuit 75 includes the phase difference voltage obtained by the phase comparator 71, the voltage obtained by the differential circuit 78, and the first F-V.
The voltages obtained by the conversion circuit 77 are added, and the addition result is added to the VCO circuit 72 as a control voltage. The oscillation frequency of the VCO circuit 72 is frequency-divided by the 1/2 frequency divider 73 and then supplied to the data reading circuit 83 as a data reading clock, and at the same time supplied to the phase comparator 71 and the 1/588 frequency divider 80. Each is entered.

As described above, the PLL circuit of this embodiment causes the oscillation frequency of the VCO circuit 72 to follow the sync pattern generation period and corrects the deviation between the 1/2 VCO frequency and the reproduction speed. Since the oscillation frequency is controlled, compared to the case where either one is controlled,
The frequency of the VCO circuit 72 can be controlled more accurately. For example, in the case of the PLL circuit of the present embodiment, a good state can be maintained even when the linearity between the input voltage of the VCO circuit 72 and the oscillation frequency is greatly deviated compared to the PLL circuits of the other embodiments.

Next, details of the sync pattern detection circuit used in the PLL circuit of each of the above embodiments will be described. FIG. 9 is a diagram showing the structure of this sync pattern detection circuit. The sync pattern is, for example, a combination of a pattern in which the H level is continuous for 11 clocks and a pattern in which the L level is continuous for 11 clocks in the EFM signal, and has a pattern length of 22 clocks in total. Therefore, the sync pattern has the longest pattern in the structure of the EFM signal.

The detection of this sync pattern is performed as follows. First, EFM is performed by the first 1/2 frequency divider 91.
One period of the EFM signal is generated by dividing the signal by a ratio of 1/2. At the same time, the EFM signal is sent to the inverter 92.
Is input to the second 1/2 frequency divider 93 through
EF of the opposite rising by dividing by the ratio of / 2
Generate one cycle of the M signal. The output of the first 1/2 frequency divider 91 is given to the first counter 94 and also given to the second counter 96 via the inverter 95. Each of the counters 94 and 96 has an EF based on the clock.
The time of the M1 cycle is counted, and the count value (clock number) is sent to the first comparator 97. On the other hand, for the output of the second frequency divider 93, the third counter 98, the inverter 99, the fourth counter 100 and the second comparator 10 are also provided.
The same process is performed by 1. Each comparator 97, 1
01 selects the larger one of the respective values fetched from the two counters and sends the selected value to the third comparator 102. The third comparator 102 selects the larger of the two input values, and uses that value as the fourth comparator 103 and the fifth comparator.
To the comparator 104 and the maximum value hold circuit 105, respectively. At this time, if the maximum value hold circuit 105 is in the initial state, the value obtained by the third comparator 102 is set as it is in the maximum value hold circuit 105. If the previous value is already held in the maximum value holding circuit 105, the fourth comparator 103 compares the newly input value with the value already held in the maximum value holding circuit 105. If the newly input value is larger, the content of the maximum value hold circuit 105 is updated with this value.

Then, this operation is executed while repeating the reset of the maximum value hold circuit 105 at almost the same time interval as the sync pattern generation cycle. Therefore, at least immediately before the maximum value hold circuit 105 is reset, the maximum value hold circuit 105 holds the value corresponding to the number of clocks of the sync pattern.

In this embodiment, the frequency division output of the EFM signal is used as the reset pulse. That is, this reset pulse is obtained by dividing the EFM signal with a division ratio such that one sync pattern is included in one cycle.

This frequency-divided signal has a maximum value holding circuit 105.
Is supplied as a set pulse to the data hold circuit 106 a certain time before being supplied as a reset pulse. That is, this divided signal is used as the data hold circuit 1
At the same time as a set pulse is input to 06, a delay device 1
07 is input to the maximum value hold circuit 105 as a reset pulse after being delayed for a predetermined time. Therefore, the value held in the maximum value hold circuit 105 is transferred to the data hold circuit 106 immediately before the maximum value hold circuit 105 is reset.

The value held in the data hold circuit 106 is output to the fifth comparator 104. Fifth comparator 1
04 compares the value input from the data hold circuit 106 with the value next input from the third comparator 102, and if the difference is within ± α, the value held in the data hold circuit 106 (clock The sync pattern detection pulse is output assuming that (number) corresponds to the sync pattern length. Here, the width of ± α is provided in order to absorb an error caused by a change in the reproduction speed such as a change in the clock frequency or the time base of the EFM signal.

When the disc is scratched, the EFM signal may stop, that is, the signal level of the EFM signal may be fixed for a long period of time. In such a case, the sync pattern cannot be detected correctly, and the correct voltage according to the sync pattern generation frequency cannot be applied to the adder circuit.

Therefore, in this embodiment, the counters 94 and 9 are used.
When the count value of 6, 98, 100 exceeds a certain value, each counter can output an overflow signal,
All counters 94, 96, 9 in the AND circuit 108
When it is detected that 8 and 100 are in an overflow state, a defect detection signal is output to the output hold circuit 109.

The output hold circuit 109 is, for example,
In the PLL circuit of each embodiment shown in FIG. 1 and FIG. 8, when the defect detection signal is input between the loop filters 18 and 79 and the adder circuits 15 and 75,
F-V conversion circuit 1 through loop filters 18 and 79
It holds the voltage input immediately before 7 and 77, and functions so that an unreasonable voltage is not input to the adder circuits 15 and 75.

Similarly, the output hold circuit 109 is
In the PLL circuit of each embodiment shown in FIGS. 5 and 8, when the defect detection signal is input between the F-V conversion circuits 47 and 77 and the differential circuits 48 and 78,
The voltage input immediately before the F-V conversion circuits 47 and 77 is held, and the differential circuits 48 and 78 function so that an unreasonable voltage is not input.

In addition to the defect detection signals (H level) from the four counters 94, 96, 98 and 100, the AND circuit 108 also provides a speed at which the disk motor can be played back when the disk motor is stopped and when the disk motor is stopped. The signal S that is at the H level is input except during acceleration to.

With this structure, even if the disc is scratched, the normal operation of the VCO circuit can be maintained, and the reliability can be improved.

[0048]

According to the first aspect of the invention, the oscillation frequency of the voltage controlled oscillator can be varied within a wide range according to the period of the synchronization pattern detected from the EFM signal. Therefore, it is possible to generate an optimum data reading clock even during a period in which the disk rotation speed does not converge to the specified reproduction linear velocity, such as immediately after the track search, regardless of the performance of the disk motor. Disc playback can be performed in a short time.

According to the second invention, the oscillation frequency of the voltage controlled oscillation means can be controlled so as to correct the deviation between the oscillation frequency of the voltage controlled oscillation means and the reproduction speed.
An optimum oscillation frequency according to the reproduction speed can be generated as the data reading clock. Therefore, as in the first aspect of the invention, it becomes possible to generate the optimum data reading clock even during a period in which the disk rotation speed does not converge to the specified reproduction linear velocity immediately after the track search, and the performance of the disk motor is improved. Regardless of this, it is possible to satisfactorily perform the disc reproduction immediately after the track search in a short time.

Further, according to the third aspect of the invention, the oscillation frequency of the voltage controlled oscillator is varied in a wide range according to the period of the synchronization pattern detected from the EFM signal, and the oscillation frequency and the reproduction speed of the voltage controlled oscillator are changed. Since the deviation is corrected, it is possible to more accurately match the oscillation frequency with the reproduction speed as compared with the case where either one is controlled.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit that generates a data reading clock in an optical disk reproducing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of an FV conversion circuit in the PLL circuit of FIG.

FIG. 3 is a diagram for explaining the operation of the FV conversion circuit of FIG.

4 is a diagram showing a variation range of an oscillation frequency of a VCO circuit in the PLL circuit of FIG.

FIG. 5 is a block diagram showing the configuration of a PLL circuit according to another embodiment of the present invention.

6 is a diagram showing a configuration of a differential circuit in the PLL circuit of FIG.

FIG. 7 is a diagram showing an example of input to the differential circuit of FIG.

FIG. 8 is a block diagram showing a configuration of a PLL circuit according to still another embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a sync pattern detection circuit used in the PLL circuit of each embodiment.

FIG. 10 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 11 is a diagram showing a variation range of an oscillation frequency in a conventional PLL circuit.

[Explanation of symbols]

 11, 41, 71 ... Phase comparator 12, 42, 72 ... VCO circuit 13, 43, 73 ... 1/2 frequency divider 15, 45, 75 ... Addition circuit 16, 46, 76 ... Sync pattern Detection circuit 17,47,50,77,81 ... FV conversion circuit 48.78 ... Differential circuit 49,80 ... 1/588 frequency divider 94,96,98,100 ... Counter 108 ... AND circuit 109 ... Output hold circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kuniyoshi Takano 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture

Claims (6)

[Claims] 1. A voltage-controlled oscillation means capable of controlling an oscillation frequency based on an applied control voltage, and a phase of an EFM signal read from a disk and an output signal of the voltage-controlled oscillation means are compared with each other. Phase comparison means for generating a voltage according to the phase difference, synchronization pattern detection means for detecting a synchronization pattern from the EFM signal, and conversion means for converting the cycle of the synchronization pattern detected by the synchronization pattern detection means into a voltage. An optical disc reproducing apparatus comprising: an addition unit that adds the output voltage of the phase comparison unit and the output voltage of the conversion unit and adds the output voltage as a control voltage to the voltage controlled oscillation unit. 2. A voltage-controlled oscillating means capable of controlling an oscillating frequency based on an applied control voltage, a phase of an EFM signal read from a disk and an output signal of the voltage-controlled oscillating means are compared, and A phase comparison unit that generates a voltage according to a phase difference, a synchronization pattern detection unit that detects a synchronization pattern from the EFM signal, and a first conversion unit that converts the period of the synchronization pattern detected by the synchronization pattern detection unit into a voltage. Conversion means, frequency division means for dividing the oscillation frequency of the voltage controlled oscillation means with a division ratio such that the period matches the synchronization pattern when the oscillation frequency is synchronized with the reproduction speed, and the frequency division means Second conversion means for converting the output frequency into a voltage; differential amplification means for amplifying a difference between the output voltage of the first conversion means and the output voltage of the second conversion means; The output voltage of the comparator means and the output voltage of said differential amplifier means by adding, an optical disk reproducing apparatus characterized by comprising an adding means for adding a control voltage to said voltage controlled oscillation means. 3. A voltage-controlled oscillating means capable of controlling an oscillating frequency based on an applied control voltage, and a phase of an EFM signal read from a disk and an output signal of said voltage-controlled oscillating means are compared, A phase comparison unit that generates a voltage according to a phase difference, a synchronization pattern detection unit that detects a synchronization pattern from the EFM signal, and a first conversion unit that converts the period of the synchronization pattern detected by the synchronization pattern detection unit into a voltage. Conversion means, frequency division means for dividing the oscillation frequency of the voltage controlled oscillation means by a division ratio such that the period matches the synchronization pattern when the oscillation frequency is synchronized with the reproduction speed, and the frequency division means Second conversion means for converting the output frequency into a voltage; differential amplification means for amplifying a difference between the output voltage of the first conversion means and the output voltage of the second conversion means; An adding means for adding the output voltage of the comparing means, the output voltage of the first converting means, and the output voltage of the differential amplifying means, and adding the added voltage as a control voltage to the voltage controlled oscillating means. Optical disk reproducing device. 4. The optical disk reproducing apparatus according to claim 1, wherein the EFM signal read by the disk is detected to be fixed for a predetermined time or longer, and the detecting section detects the EFM signal. And a holding means for holding the output voltage of the converting means immediately before that and outputting it to the adding means when it is detected that the logic level of is fixed for a predetermined time or longer. Playback device. 5. The optical disc reproducing apparatus according to claim 2, wherein the EFM signal read by the disc is detected to be fixed for a predetermined time or longer, and the EFM signal is detected by the detecting unit. Holding means for holding the output voltage of the first converting means immediately before that and outputting it to the differential amplifying means when it is detected that the logic level of is fixed for a predetermined time or longer. An optical disk reproducing device characterized by the above. 6. The optical disk reproducing apparatus according to claim 3, wherein the EFM signal read by the disk is detected to be fixed for a predetermined time or longer, and the detecting means detects the EFM signal. Holding means for holding the output voltage of the first converting means immediately before that when it is detected that the logic level of is fixed for a predetermined time or longer and outputting it to the differential amplifying means and the adding means, respectively. An optical disk reproducing apparatus, further comprising: