JPS59123937A - By-pass control system of arithmetic device - Google Patents

Abstract

PURPOSE:To improve a by-pass control circuit and to simplify the hardware by by-passing only the positive/negative sign of an arithmetic result to an operand register when the arithmtic result of a leading instruction is transferred to a data register. CONSTITUTION:A multiplexer 13 is coupled with only the positive/negative sign part 12 of an A register 2. The output line of a floating register FR1 and the by-pass line from an E bus are coupled with both circuits 13 and 14, and the by-pass line from a D bus is not coupled with the circuit 14. Consequently, only the positive/negative sign of the arithmetic result outputted from the 1st arithmetic part 4 to the D bus is by-passed to the register 12. Then, an address comparing circuit 15 checks whether the leading (n) of the arithmetic result of the leading instruction coincides with the storge location N or M of the 1st or 2nd operand of the trailing instruction and performs by-pass control when n=N or when n=M. Consequently, the by-pass control circuit is improved and the hardware is also simplified.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a control method for an arithmetic device, and in particular, in an arithmetic device, the execution result of one arithmetic instruction is used as an operand of the next arithmetic instruction. The present invention relates to a control method for a bypass circuit provided in order to shorten calculation time in a case.

[Technology background]

FIG. 1 shows the circuit configuration of a conventional arithmetic unit of the type to which the present invention is directed. In this figure, 1 is (%+1) element registers R(0).

PR(F) consisting of R(1), ..., R(s)
A data register called 1oati*g Register), 2.3 is an operand register,
2 is an A register, 3 is a B register, 4 is a first arithmetic unit that executes all LOAD-related arithmetic operations, and 5 is a second arithmetic unit that executes addition, subtraction, multiplication, and division instructions.

6.7.8 is a multiplexer, 9 is a control unit, i.

represents the D bus, and 11 represents the E bus. here.

Each register 1.2.3 is written and read simultaneously by the control unit 9.

The operation of the conventional device shown in FIG. 1 will be briefly explained below. For convenience of explanation, register element R(0) of FR
, R(1),...,R(, month is sometimes used to represent its content data.

First, regarding the calculation operation using the second calculation unit 5.

This will be explained using an example. FIG. 2 shows the time chart, from FR at tl.

Transfer R(0) to the A register and transfer R(1) to the B register. Next, in the second and third, operands R(0) and R(1) are read from the A register and B register to the second calculation unit, and the addition operation of R(0) + R(1) in ■ is executed. Then, while outputting the operation result onto the E bus and writing it to R(0) of PR, it is also written to the A register by bypassing the multiplexer 7. Two cycles are used for the operation of this second arithmetic unit.

Third, at the same time, R(1) is transferred from FR to the B register.

Next, in the fourth and fifth sections, based on R(0) of the A register and R(2) of the B register, which are the operation results of the previous ■, the second operation section calculates Rto) + R(2) The addition operation is executed, and the operation result is outputted onto the E bus again and written to R(0) of the FR. For the calculations that follow, 2
Since cycles were used, the entire operation of ■ and ■ was executed in four cycles. However, this is the above ■
The operand R(0) used in the operation is changed from PR to A
Using bypass from the E bus without transferring to the register,
By using what is written directly to the A register, the calculation time is reduced by one cycle.

To use such a bypass, the control unit 9 compares the destination address of the operation result of the preceding instruction and the operand address of the next operation instruction for sequential operation instructions, and according to the comparison result, the multiplexer 7 or This is done by controlling 8.

Next, regarding the operation of the first arithmetic unit, R (
0) -R(1) transfer will be taken as an example and explained according to the time chart in FIG. IV4. First of all, to tl (1).

Transfer R(0) from FR to A register, ! 1. ' is read into the first arithmetic unit, and at tl, it is written to R(υ) of PR.

In this case, one cycle is used for the operation of the first arithmetic unit.Function 4 of the first arithmetic unit is to manipulate the positive and negative polarity of the data. Just do it.

FIG. 5 shows a time chart for an example of an operation in which both one or more first arithmetic units and second arithmetic units are used, and the operands are also controlled.

As described above, in an arithmetic device, by using an innovation circuit, it is possible to significantly shorten the calculation time. The goal is to improve the innovation control circuit and simplify the process.

The present invention focuses on the characteristics of the bypass circuit leading from the D bus to the A register, and when the first calculation unit executes all LOAD-related instructions, it only operates on the positive and negative signs, and does not perform any operations on the data itself. Because I don't do it, LO
After all AD system instructions are executed, the result of the operation is used in the first instruction, and when the data is controlled by the first instruction, the data body of the A register is supplied to the first operation unit, while the data itself is stored in the A register as it is. This is to simplify the structure of the multiplexer circuit at the input section of the A register by bypassing only the positive and negative signs of the data stored and output from the first arithmetic unit to the D bus to the A register. .
゛The configuration of the present invention includes a data register for storing operation data, and an operand register.

The arithmetic unit detects whether the operation result of the preceding instruction is used as an operand for two consecutive arithmetic instructions, and if it is used as an operand, it is output from the arithmetic unit to the data register. In an arithmetic device that has a control circuit that bypasses the operation result to the operand register, if the preceding instruction is a LOAD instruction, the data in the operand register is stored after the preceding instruction is executed until the subsequent instruction is executed. When storing the operation result of the preceding instruction and transferring it to the data register.

This method is characterized in that only the sign of the operation result is bypassed to the operand register.

[Embodiments of the invention]

Figure 6 shows the configuration of an embodiment of the present invention. The same figure.

This circuit roughly corresponds to the circuit shown in FIG. In the figure.

1 is FR, 2 is A register, 3 is B register, 4 is 1st
arithmetic unit; 5 is a second arithmetic unit; 6 and 8 are multiplexers; 9
is a control unit, 10 is a D bus, 11 is an E bus, 12 is a sign part of the A register, 13.14 is a multiplexer, 15
1 represents an address comparison section, and 16 represents an instruction determination circuit.

Multiplexer 13 is coupled only to the sign portion 12 of the A register, and multiplexer 14 is coupled to the remainder of the A register, ie, the data body. The output line from FR and the bypass line from the E bus are coupled to both multiplexers 13 and 14, but the bypass line from the D bus is not coupled to multiplexer 14. As a result, only the positive and negative signs of the calculation results output from the first calculation unit 4 to the D bus are bypassed to the A register. In order to write only to the plus/minus sign section of the A register, it is sufficient to supply a clock only to the plus/minus sign section and not to the others.

Control for this purpose is performed by an address comparison circuit 15 and an instruction determination circuit 16 in the control section 9.

Regarding two consecutive instructions, the address comparison circuit 15
The destination of the operation result of the preceding instruction is the first operand of the succeeding instruction (including the case of a single operand) or ``)v2
Check whether it matches either the operand storage location N or M. When 1%=N or n=M, bypass control is performed.

For D bus and E bus, multiplexer 8.13
．． 14. In order to control this, it is also necessary to consider the type of preceding instruction as described below.

When s=N ■ If the preceding instruction is a LOAD type instruction, multiplexer 13 is enabled for the D bus.

(2) If the preceding instruction is a non-LOAD instruction, that is, an addition/subtraction/multiplication/division instruction, multiplexers 13 and 14 are enabled for the E bus.

(2) If the preceding instruction is a LOAD type instruction, multiplexer 8 is enabled for the D bus.

(2) If the preceding instruction is a non-LOAD instruction, multiplexer 8 is enabled for the E bus.

The above control is executed by the instruction determination circuit 16.

The clock control for the plus/minus sign part of the A register is 1%.
This is performed depending on whether the instruction is N and the preceding instruction is a LOAD type instruction.

〔Effect of the invention〕

As described above, according to the present invention, there is no need to couple the data body of the D bus to the input multiplexer of the A register, so when the data bit length is long, the input circuit of the multiplexer is simplified. The effect of reducing the amount of hardware is significant.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional arithmetic unit, and Figure 2 is a circuit diagram of a conventional arithmetic unit.
FIG. 3 is a configuration diagram of the device shown in FIG. 1, with the A register and D bus extracted, and FIGS. 4 and 5 are explanatory diagrams of the operation side. FIG. 6 is a circuit configuration diagram of an embodiment of the present invention. In the figure, 1 is FR, 2 is A register, 3 is B register, 4
1 is the first arithmetic unit, 5 is the second arithmetic unit, 6,8°13.14 is the multiplexer, 9 is the control unit, 10 is the D bus, 11 is the E bus, 15 is the address comparison circuit, and 16 is the instruction judgment circuit. represents. Patent applicant Fujitsu Ltd. Representative patent attorney Fumihiro Hase (1 other person)) Jd ya □

Claims (1)

[Claims] A data register that stores operation data, an operand register, an operation section, and detects whether or not the operation result of the preceding instruction is used as an operand by the subsequent instruction for two consecutive operation instructions, and performs the operation if it is used as an operand. In an arithmetic unit having a control circuit that bypasses the operation result output from the unit to the data register to the operand register, if the preceding instruction is a LOAD type instruction, the subsequent instruction is executed after the preceding instruction is executed. A bypass control method in an arithmetic unit, characterized in that data in an operand register is saved until the operation is completed, and when an operation result of a preceding instruction is transferred to a data register, only the plus or minus sign of the operation result is bypassed to the operand register. .