JPS59117259A - Semiconductor read only memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor lead-on IJ memory C (hereinafter referred to as ROM), and particularly relates to a semiconductor lead-on IJ memory (hereinafter referred to as ROM), and in particular, to a single output line, several insulated gate field effect transistors (hereinafter referred to as FKT) are used. ) are connected in series and the fcROM (p, o
(referred to as my vertical ROM).

Conventionally, as this type of vertical ROM, for example,
There is one as disclosed in No. 3-80931.

In such a vertical ROM, when forming aluminum wiring on the ROM, the aluminum wiring MAL- is formed vertically as shown in FIG. 1, or horizontally as shown by AL or AL. However, crosstalk occurs between the same signals with the wiring SD or wiring that intersects the aluminum arrangement ll ALt + AL2, respectively.
This may be the cause of malfunction.

An object of the present invention was to provide a semiconductor read-only memory (ROM) that can prevent crosstalk between the same signals and completely avoid malfunctions.
'(Il- is to provide.

Hereinafter, the present invention will be explained in detail according to embodiments shown in the drawings.

Figure 2 shows a semiconductor read-only memory IJ (R) according to the present invention.
FIG. 3 is a schematic wiring diagram showing an embodiment of OM), and FIG. 3 is a vertical ROM shown to facilitate understanding of the configuration of the embodiment.
FIG. 4 is a circuit diagram of a vertical ROM.

As shown in FIG. 3, the entitlement circuit of the vertical ROM is a P-channel precharge MO8F]1[i T
Qp, memory MO8F]lf! TQ, + or Qm
, and an N-channel discharge (or sampling) MOsFETQn.

Each memo IJMOSFET is made into an enhancement W or depression type according to the information to be held in each memo. In the drawing, MO8EITQ2 is made into a depression-1 type, which is connected to the drain on the symbol.
It is distinguished from the enhancement type MO8F'ET by adding an @ line between the sources. Depression type M.

EIFETs can also be considered as complete cross-wiring configurations. The gate of each memory MO8FET is coupled to the output of address decoder DC. Address decoder Do outputs decode signals al through am in response to address signals io through A1. Decode signals aL-am are alternatively set to a selection level. The selection level is set to a low level such as No Volt.

On the other hand, the non-selection level is set to a high level equal to the voltage VDD of the main power supply. Therefore, among the series-connected MOSFETs, the MOSFET to which the decode signal of the non-selection level is supplied is turned on.

In the illustrated circuit, when the clock pulse φ is set to low level, the precharge M08FETQp is turned on in response, and the output terminal OUT is precharged to the high level of the power supply voltage. Next, when the clock pulse φ is set to high level, the precharge MOS F Fi T
Qp is turned off and discharge MO8FKTQn
is turned on. For example, if the decode signal aI is set to a selection level during precharging, then the memory IJMO-EI FET Q is turned off accordingly. Therefore, even if the discharge MO8FETQn is turned on, a current path is formed between the output terminal OUT and the ground point, which is dangerous. In this case, the output terminal OUT is maintained at a precharge level, that is, a high level. On the other hand, if the decode signal a2 is set to the selection level, the level of the output terminal OUT will be as follows. That is, in this case, MO8FFliTQ to which decode signal a is supplied
Since g is of the depression type, it remains on all the time. So series connected notes! j M OS
Since all of the FETs are turned on, when the discharge MO8FKTQn is turned on, a current path is formed between the output terminal OUT and the ground point.

As a result, the output terminal OUT is set to a low level.

In this way, the output terminal OUT outputs the selected memo IJM
The level is determined by the OS FET mode. The compressed ROM can be configured as a common semiconductor region with the source region and drain region of MO8F'ETs connected in series, and the gate! Since the pole can be used as a cross wiring that substantially covers one part of the drain/source path, it can be made relatively compact.

However, since each of the memory MO5FETs has an unavoidable resistance, for example, as the number of bits of the address signal increases, the series connection of the memory MO5FETs
Increasing the number of F 18 'I' will increase the discharge M
It takes a long time from when O8FETQ,o is turned on until the level of the output terminal OUT is determined. In other words, in this case, the operating speed becomes slower.

The operating speed of vertical ROM is the memory M O connected in series.
This is possible by reducing the number of 8FETs. According to one way to do so, they should be connected in series.
A plurality of memo IJMOSFETs are divided into a plurality of groups each forming an output signal, and one output signal is formed by logically synthesizing the output signals of each group. According to another method, memory cells to be connected in series are divided into groups, and each group is coupled to one output via a switch element (column switch) that is switch-controlled by an address signal. .

The vertical ROM of the embodiment shown in FIG. 4 employs the above two methods. In addition, in the same figure, MO8FI! ! T is indicated by a circle. Precharge MO8FII
I! T and discharge MO8FFiT are marked with side lines and indicated by dotted circles.

However, in order to prevent the drawing from becoming complicated, the depression MO8FI! ! MO8'PFfT like T is omitted. The drain-source path of the MO5FEiT connected in series is indicated by a dash-dotted line. tf
The C-input cashier line, ie the line to which the gate of the MO8FET is coupled, is shown by a solid line. Each element and wiring in the figure corresponds to the arrangement of each element and wiring formed on a semiconductor substrate by the process technology. However, the wirings A and L are connected to the drain and source paths L&l and La□ as shown in the figure.
Rather than being sandwiched between and extending parallel to them, it should be understood that they are extended in a form such as the dashed lines in FIG.

In the figure, one output, e.g. Memo IJM O8F
KT is further divided into parts to form a drain-source path, for example Lal to Lapk. Each drain-source path example λ is LaI or L
a first common output point OUT corresponding to PLp, respectively;
A column switch M0 day FET Male to Map is arranged between the two. Common output points 0UTa and 0UT
b is coupled to the input of the logic synthesis circuit G.

Drain/source path L in memory array MA4
Column switches MO8FT3TMa to Map for selecting a, + to Lap are supplied with column switch signals Ca to Cap whose selection level is set to high level and which is alternatively set to the selection level. Similarly, the drain/source path Lb.

Column switch MOE to select from Lbp k
Column switch signals CaI to 01Lp are also supplied to IFETMb+ to Mbp, respectively. The column switch signals Cal to Cap can be formed by a decoder (not shown) that completely decodes some of the address signals.

In addition, as shown in FIG. 5, the address signal A of true and doubt level
j + Aj or Ak MO8FET receiving Ak
The drain/source path can be directly selected by M or M4. In this case, a decoder as described above is not required.

Memory array MAa-((constituting memory MOB F
Decode signals al to aZ are supplied to ET, and memory array MA1)'((-constituting memory MO8F
Nine decode signals a to aγ are supplied to KT.

7+1 According to this configuration, one output terminal OUT has (r)×
The held information of one selected MO8FEIT among the (p) memory MO8FETs is output.

If the output line AL of the memory array MAb is different from the above-mentioned case and extends parallel to the drain and source paths and is coupled to the logic synthesis circuit G, the following problem occurs.

That is, in this case, an undesired coupling capacitance H1 is formed between the output line AL and the drain/source paths La1 and La2. Therefore, the passage Lal or L
a, is column switch MO8FFiTMal or Ma2
The precharge M is then discharged through the precharge M
When these paths are discharged by turning on OS FF+T, the output line AL will be lowered in potential by the desired coupling capacitance.

The output MALO violet level decreases depending on which of the address signals a1 to aZ is set to the selected level. In other words, it depends on which part of the passage LaI and La snow is discharged.

If such an undesired potential drop that occurs on the output line Lout is large, the logic synthesis circuit G1 will malfunction.

Note that undesired coupling capacitance can be reduced by sufficiently increasing the distance between the output line AL and the paths LaI and La2, but in this case, the integration density is reduced. In the configuration of FIG. 4, for example, by inverting the pattern on the memory array MA side, the logic synthesis circuit Get memory array M
It can be provided between Aa and MAb. in this case,
Since the output i1A L' does not need to be extended onto the memory array MAa, the above coupling capacitance can be ignored.

However, in this case, memory arrays MAa and M
In an appropriate circuit placed outside Ab, logic@configuration circuit G,
The problem is the output wiring for supplying the output.

In this actual example, aluminum is arranged on the vertical ROM.
When forming Lk, the aluminum wiring AL is oriented so as to intersect with the wiring STl$- and the wiring pattern in the shading direction.

Therefore, in this embodiment, the aluminum wiring A
L is the wiring arrangement B D ”+ * is each one of the wiring
Since the aluminum wiring AL intersects another wiring SD or L one after another in the direction of the arrow without being oriented in parallel with the main line and adjacent to it, the aluminum wiring AL is This prevents the occurrence of parasitic capacitance due to coupling with only one specific wire, and prevents crosstalk between the same signal and any of the above wiring EID signals.

In other words, in the case of this embodiment, the aluminum wiring AL is strongly capacitively coupled only to a specific one of the layouts v#EID or a specific one of the wirings, and the Because of the concentration of parasitic capacitance in the wiring SDj, there is no crosstalk between the aluminum wiring MAL and one wiring SD or L, and the parasitic capacitance is
As a result, a large parasitic capacitance is often generated between the aluminum arrangement AL and the wiring 8D or L.

As a result, according to this embodiment, since crosstalk can be prevented, it is possible to prevent malfunctions from occurring.

6 to 8 are cross-sectional views of a semiconductor integrated structure showing the state of formation of aluminum wiring according to the present invention. FIG. 6 is a cross-sectional view of the semiconductor integrated structure in the source-drain direction, and FIG.
A sectional view taken in a direction perpendicular to FIG. 6 between the drains,
FIG. 8 is a sectional view of the gate portion as well.

In this cross-sectional structure, the substrate 1 has a P-type structure, and an N-type frame region 2 is formed on its upper part, and a gate insulating film 3 is formed on the upper side between each NW region 2. On the insulating film 3 is a gate electrode 4 made of a polysilicon layer.
is provided, and an insulating film 5 made of Sin or a similar film is further formed above it. In addition, in Fig. 4, the reference numeral 6
indicates field 5102 membrane.

The aluminum wiring AL is formed on the insulating film 5 in a plan view and in a direction parallel to the cross-sectional direction of the insulating film 5 or the gate electrode 4 or the like.

Therefore, according to such an aluminum wiring structure, as described above, the aluminum wiring AL and the other wiring s
D'47H prevents crosstalk between the same signal as L, and can prevent malfunctions from occurring.

Note that the present invention is not limited to the above embodiments,
Various other modifications are possible; for example, the angle of inclination of the aluminum wiring with respect to other wiring is not limited at all.

As explained above, according to the present invention, since the aluminum wiring on the ROM is formed in the direction of the body with respect to other wiring, the same signal can be transmitted between the aluminum wiring and the other wiring. Crosstalk can be prevented from occurring and malfunctions can be avoided.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view of a conventional aluminum wiring deposit; FIG. 2 is a schematic plan view of an embodiment of aluminum wiring in a semiconductor read-only memory according to the present invention; FIG. 3 is a circuit diagram of a vertical ROM; FIG. 4 is a circuit diagram of the vertical ROM of the embodiment, FIG. 5 is a circuit diagram of a column switch circuit, and FIG. 6 is a source of a semiconductor integrated structure showing the formation state of aluminum wiring in the present invention.
FIG. 7 is a cross-sectional view of the drain direction, FIG. 7 is a cross-sectional view of the source-drain distance taken in a direction perpendicular to FIG. 6, and FIG. 8 is a cross-sectional view of the gate portion. AL...aluminum wiring, SD...wiring, L...
·wiring. -de--1

Claims (1)

[Claims] 1. A semiconductor read-only memory formed on the same substrate by a vertical ROM, characterized in that aluminum wiring on the ROM is formed in a direction larger than other wirings.