JPS59108460A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a solid-state image pickup device with less signal interference between picture elements by connecting a photo sensing transistor (TR) receiving incident light in series with a readout TR reading out selectively a photoelectric converting output and arranging these TR to each cross point of a matrix. CONSTITUTION:Sources of photo sensing SIT of solid-state image pickup elements 40-1, 40-2... are connected to a common reset line 41, to which a bias voltage Vs is applied. Further, a gate of SIT for readout of one element group arranged in X direction is connected to a vertical selection shift register 43 via row lines 42-1, 42-2.... A drain of SIT for readout of the element group in one string arranged in Y direction is connected similarly to a horizontal selection shift register 45 via column lines 44-1, 44-2.... Further, a voltage V0 is applied to a video line 47 via a load resistor 48 and time series picture information is obtained at a terminal 49 based on a control signal from each register.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device. - Conventional solid-state imaging devices that use charge transfer devices such as OOD, and devices that use MOS (MOS) transistors are widely used. However, these solid-state imaging devices have problems such as leakage during charge transfer, low photodetection sensitivity, and low degree of integration. Static induction transistors (5tatiOIn6uation Transistors) can be used to solve these problems all at once.
A new method using the SIT (SIT, an acronym for Lstor) has been proposed. For example, Japanese Patent Application Publication No. 55
No. 15229-1 discloses a solid-state imaging device in which the sources of SITs arranged in a matrix are connected to row conductors, the drains are connected to column conductors, and the gates are connected to clear conductors. Furthermore, as a further development of such a solid-state imaging device, one in which a container is connected to the gate is considered. FIG.

As shown in FIGS. 1A and 1B, the SIT
At the same time as forming an n-type buried layer 2 constituting a source of
A rough P+ gate region 5 is formed. The diffusion depth of the drain region 4 is made shallower than that of the gate region 5 in order to ensure the opening and closing of the channel region formed between the drain region 4 and the source region 2. A drain electrode 6 is bonded to and provided on the gate region 5, and a gate electrode 8 is provided on the gate region 5 with an insulating layer 7 interposed therebetween.
A gate capacitor is formed by forming an IS structure. Further, adjacent SITs are electrically isolated from each other by providing an insulating layer 9 between them so as to separate the epitaxial layer 8.

In such a configuration, if the gate region 5 is set to a reverse bias of M with respect to the source region 2 in a steady state with no optical input, the channel region is depleted, so that the source-drain region is forward biased. Even if the current does not flow between the source and drain. In such a state, when hole-electron pairs are generated by optical input, the electrons are accumulated or expelled toward the source region 2 or the I/drain region 4, and the holes are accumulated in the gate region 5 and connected to the gate by the MIS structure. Charge the capacitor and change the gate potential by ΔvG. Here, the sum of the capacitance of the gate capacitor, the capacity of the depletion layer for the epitaxial layer 8, and -... is 0.
If the amount of charge generated by optical input and accumulated in the gate region 1 region 5 is QL, then ΔVo=QI,/,o. When a gate read pulse φG is applied to the gate electrode 8 after an accumulation time of
It's like adding vo.

Then, the potential between the gate region 5 and the drain region 4 decreases, the depletion layer decreases, and a drain current corresponding to the optical input flows between the source and the drain. This drain current is SI
Due to the amplification effect of T, Δvo is multiplied by the degree of amplification and becomes large. 11. .

Furthermore, even if the source and the rain of the SIT are exchanged, the same operation will occur.

FIG. 2 shows a circuit configuration of a solid-state imaging device constructed by arranging the above-mentioned SITs in a matrix, and FIG. 2B similarly explains its operation.

FIG. Each 5ITIO-1,10-
2... is the normally-off type n-channel BIT mentioned above, and outputs the output video signal for the optical input by XY.
It is read using the address method. The sources of the JTs constituting each pixel are connected to the common reset-1 line 11 to apply a bias voltage v8, and the gates of the SIT groups in one row arranged in the X direction are connected to the row line 12-1. 12-
2... is connected to the vertical selection shift register 1B. In addition, the drains of the SIT groups in one row arranged in the Y direction are connected to the column lines 14-1, 14-2, etc., and the other column lines are selectively driven by the horizontal selection shift register 5. The video line 17 is connected to the video line 17 through horizontal selection transistors 6-1, 16-2...
Commonly connected to.

A voltage V is applied to this video line 17 via a load resistor 18. Now, set the bias voltage vs to the reset line 11 appropriately, for example, to zero volts, and read out the output of one SIT pixel. Let's think about a case where this happens.

For example, input 1 is performed from vertical selection shift register 8.
When the horizontal selection transistor 6-IKi output pulse φD□ is applied from the horizontal selection shift register 5 to the horizontal selection transistor 6-IKi during the period when the row selection pulse φG1 is supplied to the line selection transistor 2-1, 3IT10
-1 is selected, and this 5ITIO-1 has a load resistance of 18
, video line 17, horizontal selection transistor 6-1
and a drain current flows through the column line 14-1,
An output voltage ■out is generated at the output terminal 19. As described above, this drain current is a function of the gate voltage, and since this gate voltage is a function of the optical input, the □ increase Δvout from the output voltage in the dark becomes a voltage corresponding to the optical input. Moreover, this voltage Δ■out becomes a large value, which is ΔvG multiplied by the amplification degree, due to the amplification effect of the SIT. Next, a read pulse φDz" is applied from the horizontal selection shift register 5 to the horizontal selection transistor 16-2, and S I T
``'10-2 is read out, and when the reading of -digits is completed, the row selection pulse φG2 is applied to the next row from the vertical selection shift register 8, and 13IT of that row is read out one by one.

However, in the solid-state imaging device described above, 1 is
When the intensity of the incident light is high, QL becomes very large and ΔvG
becomes higher, and with respect to the initially set reverse bias value V, v
G+Δ■G (ΔvG〉0) is the set source potential v of SIT
When the pinch-off voltage V for s is exceeded, its SI
Even if T is not selected, this current becomes undesirably conductive and flows from the other selected row line □.The current flows along with the signal current through the same column line, and the current flows between the pixels. There is a problem that causes signal interference. For this reason, such solid-state imaging devices have limitations on the amount of exposure, and are limited in practical terms.

An object of the present invention is to solve the above-mentioned problems and provide a solid-state imaging device appropriately configured to effectively read out each pixel signal without causing signal interference between pixels even when the intensity of incident light is high. This is what I am trying to do.

The solid-state imaging device of the present invention has a photosensitive transistor that receives incident light and a readout transistor that selectively reads out the photoelectric conversion output of this photosensitive transistor, and their main current paths are connected in series. A solid-state image sensor made of
A readout transistor of the solid-state image sensor is provided at each intersection of a matrix composed of a plurality of row lines and a plurality of column lines, and a readout transistor of the solid-state image sensor is connected to the row line and column line, and the photosensitive transistor is connected to a reset line. It is characterized by:

The present invention will be described in detail below with reference to the drawings. 'FIGS. 8A and 8B are a sectional view and a plan view showing the structure of an example of a solid-state imaging device used in the solid-state imaging device of the present invention. In this example, both the photosensitive transistor 21 and the readout transistor 22 are formed on the same substrate as an SIT structure.

That is, an n+ buried layer 24 constituting the drain region of the photosensitive 5IS2] and the source region of the readout 5IT22 is formed on the P-type substrate 28, and an n- epitaxial layer g5 is formed on the substrate 28 and the buried layer 24. The n source region 26 and the P+ gate region 27 constituting the photosensitive 5IT 21 and the n+ drain region 28 and the P+ gate region 29 constituting the readout SIT'2 are heated on the surface of the epitaxial layer 25, respectively. Formed by a diffusion method or the like. 1SIT21 for photosensitive and 5IT22 for continuous printing are connected to the drain region of 5IT21 and 5I
Except for configuring the source region of T2B with a common n+ buried layer 24, it is electrically isolated by an insulating layer 80 provided from the n+ buried layer 24 to the surface of the epitaxial layer 25. Their main current paths are connected in series □, and a P-type substrate 2 is connected between adjacent solid-state image sensors.
An insulating layer 80 is similarly provided from B to the surface of the epitaxial layer 25 to electrically isolate them from each other. SI' for photosensitive
A source electrode 81 is connected to the source region 26 of 141, and u-th is connected to the drain region 28 and gate region 29 of the read SIT 2g.

A drain electrode 82 and a gate electrode 8B are connected to each other, and the other surfaces are covered with a surface insulating film 84. That is, in this example, the photosensitive SIT 21 is not provided with a gate electrode. Therefore, since there is no loss in the amount of transmitted light due to the gate electrode, short wavelength sensitivity can be improved.

In addition, as in this example, 5IT21 for photosensitive and 5ET for reading
Separation from 22 and these photosensitive SIT and readout SI
By separating the solid-state image sensing elements consisting of T by using the insulating layer 80, their electrical isolation can be almost completely achieved, resulting in good current controllability and amplification characteristics.

41st figures A and B are a cross-sectional view and a plan view showing the structure of another example of the solid-state imaging device used in the solid-state imaging device of the present invention. In this example, the separation between the photosensitive 5IS 21 and the continuous output 5ET 2.2 and the solid-state image sensing device consisting of the photosensitive BIT and the readout SIT is performed using an n-epitaxial layer instead of the above-mentioned insulating layer 80. 25, a P+ isolation gate region 86 is formed, an isolation gate electrode 87 is bonded to this isolation gate region 86, and a predetermined voltage is applied to this isolation gate electrode 87. Epitaxial layer z5 below 86
The only point where the depletion layer is formed in the first
This book is different from the one shown in FIG. 8, and the same reference numerals as those shown in FIG. 8 represent the same things. An isolation gate region 86 is formed in this manner, and a depletion layer formed by applying a voltage to the isolation gate region 86 isolates the elements and electrically connects the photosensitive SIT? In the case of separation, there is an advantage that the density of elements can be increased.

FIG. 5 is a circuit diagram showing an example of the configuration of a main part of the solid-state imaging device of the present invention. In this example, a plurality of solid-state imaging devices shown in FIG. 8 or 4 are formed in a matrix on the same substrate. Each □solid-state image sensor 40-
1.40-2. The sources of the photosensitive SITs are connected to the common reset line 41, a bias voltage V is applied, and X
The readout SIT gates of one row of element groups arranged in the row line 42-1, 42-2. ... is connected to the vertical selection shift register 4B. In addition, the drains of the readout SITs of one row of element groups arranged in the Y direction are connected to the columns 44-1, 44-2. ..., and each of these column lines is connected to a horizontal selection shift register 45.
Horizontal selection transistor 4 selectively driven by 1□′
6-1.46-2. . . are commonly connected to the video line 47 via... A voltage V is applied to this video line 47 via a load and a resistor 48. f: is applied, and the vertical selection shift register 4B and horizontal selection shift register 451 are controlled in the same manner as explained in FIG. 2, so that time-series pixel information is obtained from the output terminal 49.

In this configuration, if a certain column line is selected,
Reading out a column of elements connected to that column line (7
Among the readout SITs, except for the readout SIT of the element whose row line is selected □, the other readout SITs have the gate potential of the photosensitive SIT connected in series with it rise to reach the pinch-off level or higher. However, since a high drain potential is not applied via the read SIT,
No current flows, so no signal interference between pixels occurs. Also, at this point, the gate potential of the photosensitive SIT further rises, and the fixed beam accumulated in the gate region is biased in the forward direction by 1° with respect to its source potential (bias voltage vs. applied to the reset line 41). Even if more holes are ejected through the source, they will not turn on the photosensitive SI'l'. In addition, to reset the element, use reset + IJ.
By lowering the bias voltage v8 applied to 41 in a pulse manner and forcibly biasing the source 1 to drain of each photosensitive SIT in the forward direction, it is possible to perform the same operation on all the elements at the same time.

In this example, even if the intensity of the incident light is high and the gate potential of the photosensitive SIT exceeds the pinch-off level,
Unless I'l' is selected, this --... read S
Since no current flows through the sensor T and photosensitive SIT, no unwanted signal interference between pixels occurs. Furthermore, as shown in FIGS. 8 and 4, the photosensitive SIT of each element is not provided with a gate electrode and is made floating to receive incident light. There is no transmission loss of short wavelength components, and therefore the spectral characteristics can be improved.

Note that the present invention is not limited to the above-mentioned example, and can be modified in many ways.8 For example, in the above-mentioned example, the photosensitive and readout transistors constituting the solid-state image sensor are each provided with an SIT. However, each of these can also be configured with a field effect transistor (FET), or one can be configured with an SIT and the other with a field effect transistor (FET).
It can also be constructed using FETs. Further, these transistors are not limited to n-channel type transistors, but may also be configured as n-channel type transistors. Furthermore, in FIGS. 8 and 4, the drain region of the photosensitive SIT 21 and the readout 5
By forming the source region of the IT2m with a common n-buried layer 24..., the main current paths of the photosensitive 5IT21 and the readout SIT22 were connected in series. Connections can also be made by other methods, such as forming them separately and electrically connecting them.

Furthermore, in FIG. 5, all the solid-state image sensors 40-
1.40-1. Although the sources of the photosensitive SITs of .

As described above, according to the present invention, each pixel signal can be effectively read out without causing signal interference between pixels even when the intensity of incident light is high, so the exposure amount is not limited. do not have.

[Brief explanation of drawings]

1A and B are a sectional view and a plan view showing the structure of the SIT; FIGS. 2A and B are a circuit diagram and a signal waveform diagram for explaining the structure and operation of a solid-state image device using the SIT; 8A and 8B are a sectional view and a plan view showing the configuration of an example of a solid-state imaging device used in the solid-state imaging device of the present invention, and FIG. 4A and B are a cross-sectional view showing the configuration of another example. Figures and Plan Views FIG. 6 is a circuit diagram showing an example of the configuration of a main part of the solid-state imaging device of the present invention. 21... SIT for photosensitive 22... SI for reading
'l'2B...p-type substrate 24...n buried layer 25...n-epitaxial layer 26...n source region 27.29...p gate region 28...n drain region 80 ...Insulating layer 81.
...Source electrode 82...Drain electrode 8B...
・Gate electrode 84...Surface insulating film 86-...p
Separation gate region 87... Separation gate electrode 40-1.4
0-2...Solid-state imaging device 41...Reset line 4
2-1.42-2...Row line 48...Vertical selection shift register 44-1.44-2...Column line 45...Horizontal selection shift register 46-1.46-2... Horizontal selection transistor 47
...Video line 48...Load resistor 49...Output terminal. Patent Applicant: Olympus Optical Industry Co., Ltd. Applicant: Jun Nishizawa - Figure 1 Figure 2 ψDf-Ro-→→R-Yo. Figure 5 Procedural Amendment Document March 8, 1980, Display of Case 1982 Patent Application No. 217753: 0 Name of Invention Solid-state Imaging Device, Person Making Amendment Relationship to Case Patent Applicant (037) Olympus Optical Industry Co., Ltd. Nishizawa
Jun - Target of amendment Contents of amendment in the "Detailed Description of the Invention" column of the specification (as attached) 1 "Element J?i:r photosensitive 5
ITJ, and on the 15th and 16th lines of the opposite page, ``source-drain'' is corrected to ``1 gate-source''. (2) 313-

Claims (1)

[Claims] 1. A solid-state image sensor comprising a photosensitive transistor that receives incident light and a readout transistor that selectively reads out the light weight conversion output of this photosensitive transistor, and whose main current paths are connected in series. , are provided at each intersection of a matrix consisting of a plurality of row lines and column lines, and the 1" continuous output transistor of the solid-state image sensor is connected to these row lines and column lines, and the photosensitive transistor is connected to the reset line. A solid-state imaging device characterized in that: