JPS5872870U - hybrid integrated circuit - Google Patents
hybrid integrated circuitInfo
- Publication number
- JPS5872870U JPS5872870U JP16782381U JP16782381U JPS5872870U JP S5872870 U JPS5872870 U JP S5872870U JP 16782381 U JP16782381 U JP 16782381U JP 16782381 U JP16782381 U JP 16782381U JP S5872870 U JPS5872870 U JP S5872870U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- chip
- type capacitor
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の混成集積回路を示す斜視図、第２図は本
考案の実施例を示す斜視図、第３図ａ。
ｂは夫々接着剤の塗布状態を説明するための説明図であ
る。
図面中、１は基板、１ａは導体パターン、２はチップ形
コンデンサ、２ｂは電極部、３は接着剤である。FIG. 1 is a perspective view showing a conventional hybrid integrated circuit, FIG. 2 is a perspective view showing an embodiment of the present invention, and FIG. 3a. b is an explanatory diagram for explaining the application state of the adhesive, respectively. In the drawings, 1 is a substrate, 1a is a conductor pattern, 2 is a chip capacitor, 2b is an electrode portion, and 3 is an adhesive.
Claims (1)
接着面と基板上に形成された導体パターンとが導電性の
接着剤を介して接着されてなる混成集積回路において、
チップ形コンデンサを接着するのに必要な最小限度の面
積で且つ前記接着面における端部側の部分に前記接着剤
を塗布してチップ形コンデンサを導体パターンに接着し
たことを特徴とする混成集積回路。In a hybrid integrated circuit in which the bonding surfaces of electrode parts formed at both ends of a chip-type capacitor and a conductor pattern formed on a substrate are bonded via a conductive adhesive,
A hybrid integrated circuit characterized in that the chip-type capacitor is bonded to the conductor pattern by applying the adhesive to the minimum area necessary for bonding the chip-type capacitor and to the end portion of the bonding surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16782381U JPS5872870U (en) | 1981-11-11 | 1981-11-11 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16782381U JPS5872870U (en) | 1981-11-11 | 1981-11-11 | hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5872870U true JPS5872870U (en) | 1983-05-17 |
Family
ID=29959893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16782381U Pending JPS5872870U (en) | 1981-11-11 | 1981-11-11 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5872870U (en) |
-
1981
- 1981-11-11 JP JP16782381U patent/JPS5872870U/en active Pending
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