JPS5848135A - Data bus control system - Google Patents

Abstract

PURPOSE:To obtain high efficiency of utilization of a common bus by allowing all computers to use the common bus exclusively in the same way without any special computer for controlling the right of exclusive use of the common bus, and sending only significant data through the common bus. CONSTITUTION:A computer with an address (i) holds a bus exclusive-use line at ''L'' synchronously with the (i)th rise of the 1st clock signal counted from a rise of the 2nd clock signal. The computer, once holding an address tag line at ''L'', sends a destination address AD to a data line and then holds a data tag line at ''L'' to send transmitted data DT to a data bus. A reception-side computer detects its own address on the data line synchronously with the address tag line, and fetches the data DT while the data tag line is at ''L''. After the reception, the result of a parity check on the received data is sent to the data line synchronously with an answer tag line. The transmission-side computer stops driving the bus exclusive-use line when the answer shows normalcy.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data bus control system, in which data is transferred between computers or equivalent devices connected to a common path consisting of a plurality of signal lines, and in particular, all computers use the same method. This field is concerned with data bus control methods that can monopolize a common path and perform high-speed data transfer through simple agreements.

An example of data transfer in a conventional data bus control system will be explained using FIG. 1. In FIG. 1, 1 is a common path, and A1. Bt and 01 are computers that transfer data via the common path l, and r)l is a path control computer. The common path 1 is composed of a plurality of data lines and a plurality of control lines for transferring data between computers connected thereto. Computer AI, BL
, 01, when transmission information is generated, monopolizes the common path 1 with permission from the path control computer D1 at an appropriate time, attaches a destination address to the data, and sends the data in bytes or words to the data line of the common path 1. do. Also computer AI.

Bl, 01 constantly monitors the data on the common path l, ignores it if it is not addressed to its own station, and takes it into its internal memory if it is addressed to its own station.

The bus control computer power may have the same operations as the computers AI, Bl, and 01, but also controls the entire system to determine which computer is given the right to exclusively use the path. There are various ways to grant exclusive rights to a path, such as the following. In other words, the path control computer sends special information defined as a polling message to one computer in the system.@Each computer ignores the polling message if it is not addressed to its own station, but if it is addressed to its own station, it ignores the polling message. You can get exclusive rights to the bus at this point. If a computer that has obtained bus exclusive rights has transmitted data at that time, it can attach an appropriate destination address and send the data to the common path. Once the computer has finished transmitting the data, it will give up exclusive rights to the path in some way.
Notify the control computer. Furthermore, when the computer receives the polling message, if there is no data to be sent, it will not transmit data and immediately relinquish its exclusive right to the bus.

When the path control computer learns that the computer that sent the polling message has given up exclusive rights to the bus, it sends the polling message to a different computer. In this way, a plurality of computers transfer data via a common path according to instructions from the path control computer.

Another conventional method is to use a path control computer to
Instead of sequentially issuing polling messages, there are systems in which a computer that has all the data to send interrupts the path control computer using an appropriate signal line within the common path, and solicits something equivalent to a polling message.

In this way, when a plurality of computers transfer data via a common path, a special computer usually exists in order to give the computer exclusive rights to the bus.

However, according to each of the above-mentioned conventional systems, since there is only one bus control computer with a special function in the system, if the bus control computer fails, the entire system will fail. Another disadvantage is that the procedure for assigning a path exclusive tank to each computer is troublesome, resulting in wasted time.

The present invention eliminates the above-mentioned drawbacks, and eliminates the need for a special computer to control the dedicated tank of the common bus, allowing all computers to monopolize the common bus using the simple and same method. It is an object of the present invention to provide a data bus control method that enables data transfer between computers and allows a high common bus utilization rate to be obtained by allowing only valid data to flow through the common bus.

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 2 and subsequent figures. FIG. 2 shows a block system diagram of an embodiment of the data bus control method according to the present invention.

In FIG. 2, 2 is a common bus according to the gist of the present invention, and 3 is a common bus according to the gist of the present invention.
is a clock generator. A2, B2.

02 and D2 are computers that transfer data via a common bus.

The common bus 2 has two different clock lines, one path dedicated line, one address tag line, one response tag line, 1,
It consists of 9 data lines including a line for book parity check. The clock generator 3 drives two different clock lines among these nine data lines. Next, the signal lines of the common bus 2 will be explained.

The first clock line synchronizes the operation of the common bus 2 and is driven by the clock generator 3. All computers perform operations related to data transfer in synchronization with this clock.

The second clock line is a clock line obtained by dividing the frequency of the first clock line by N, and is driven by the clock generator 3 to provide timing for allowing each computer to monopolize the common bus 2 without contradiction. The frequency division ratio N can be changed depending on the system.

Here, if the number of computers connected to the common bus 2 is M, then M≦N must be satisfied.

The path private line is constantly monitored by each computer, and for example, if the logic is made significant, the spring private line is significant 'L'.
In this case, it is not possible to obtain a dedicated tank for the common bus 2.

When this bus exclusive line is at "H", this path exclusive line can be driven to a significant 'L' level at a timing unique to each computer determined by clock 'H' and clock 'L'. The computer that drives this path private line to "L" obtains a private tank for the common bus 2, and can transmit data.

The address tag line is driven to L1 by the computer that has exclusive use of the common bus 2. At the same time, the destination address is sent to nine data lines.The data tag line is set to "L" after the computer that has exclusive use of the common bus 2 sends the destination address.
driven by Note that transmission data is sent out at the same time.

The response tag line is driven by the computer on the receiving side, and when the computer on the sending side finishes sending data, the response tag line becomes 1L.
response information is sent to the data line at the same time.

The data line is a line for transferring address data and response information, and includes one line for parity check.

Each line from the path exclusive line to the data line is connected to each computer by a circuit configuration such as an open collector, and the value of the signal line is the wired-OR value of the signal output from each computer. Therefore, when any one computer outputs a significant "L" signal, that signal line becomes 1L, and the other signal lines become 'H'.

Next, how a plurality of computers monopolize a common bus and transfer data without a bus control computer will be explained with reference to FIG. FIG. 3 is an example of a time chart for explaining data transfer according to the method of the present invention.

In FIG. 3, the one-dot chain line is the signal that drives the clock generation circuit 3, the solid line is the signal that drives the computer that transmits data, and the two-dot chain line is the signal that drives the computer that receives data. AD indicates the destination address, DT indicates the transmission data, and R1 indicates response information 1.

Here, a unique address i is assigned to a computer connected to the common bus 2 under the following conditions.

0≦i≦M−1 Here, as mentioned above, M is the number of computers connected to the common bus 2, and there is a relationship that M≦N with respect to the division ratio N of the clocks “Hm and ’L”. .

For example, the bus exclusive line indicating that the computer has exclusive use of the common bus 2 can be driven to "L" at the following timing. That is, the computer at address i can set the bus dedicated line to 'L' in synchronization with the i-th rising edge of the first clock signal counting from the rising edge of the second clock signal. Once the bus exclusive line is set to "L", the path exclusive tank cannot be obtained until it returns to "H".

In the meantime, since all the computers have different addresses, the timing for setting the dedicated bus line to 1L# is different. Also, while the dedicated bus line is "L", other computers are in a standby state, so two computers will not monopolize the common bus 2 at the same time.In the example shown in Figure 3, This example shows a case where the computer with address i = 3 monopolizes common bus 2, and the division ratio of the first clock signal and the second clock signal is 4, so the computer with address i = 3 is connected to common bus 2. The number of computers used is limited to four or less.

The computer that has set the bus exclusive line to "L" first drives the address tag line to "L" and at the same time sends the destination address AD to the data line, then sets the data tag line to "L" and transmits. Data DT is also sent to the data bus.

On the other hand, the receiving side computer detects its own address on the data line in synchronization with the address tag line, and then imports the data on the data line into the internal memory while the data tag line is significant "L2".After the reception is completed, the received data The result of the parity check is sent onto the data line in synchronization with the response tag line.

If the response result is normal, the sending computer stops driving the dedicated bus line and abandons the dedicated bus tank. Since the bus exclusive line is a wired OR, it becomes 1H#, and from this point on, other computers are also given the opportunity to exclusively use the bus. If the response result is an error, you can continue to retransmit with the bus exclusive line set to L1, or you can abandon the bus exclusive line and notify the software that an error has occurred, and take further action. can be left to software.

In this way, according to the above method, multiple buses can share the common bus 2 and transfer data to each other, and there is no need for a bus control computer that performs complicated bus exclusive control within the system. Bus-specific control operations can be performed using a computer with common and simple functions added. Therefore, failure of one computer does not lead to failure of the entire system, and bus exclusive control is performed by rough and simple agreements, so there is no wasted time such as polling messages, and high transfer efficiency is achieved.

Note that in the above embodiment, if the sending computer obtains a dedicated bus, the address and data are unilaterally sent regardless of the status of the receiving computer, which may cause the following problems. . That is, assume that odd computer A2 sends data to computer B2, and computer B2 returns a response indicating that it has been successfully received.

Computer A2 abandons the exclusive bus tank, but then computer C2
Suppose that computer B2 acquires the exclusive bus and sends data to computer B2, but if computer B2 has not yet finished processing the data received from computer A2, it will not be able to accept data from computer C2. will be thrown away. Computer C2 performs retransmissions, so the data will be transferred eventually, but it is undesirable from the viewpoint of bus utilization to transfer such useless data, and it becomes a problem especially when the data length is long. In order to solve this problem, another embodiment shown below adds another function to each computer. That is, after the sending computer sends out an address in synchronization with the address tag line, it does not immediately proceed to data transfer, but waits for a response from the receiving computer. Also, the receiving computer immediately responds by sending out information on the data line in synchronization with the response tag signal to determine whether or not its own station is in a state where it cannot accept data. Based on this response, the sending computer can select whether to send the data or give up the exclusive bus for data sending.

FIG. 4 is an example of a time chart for explaining data transfer using the above method. In the figure, R2 is response information 2 indicating whether reception is possible, and the other symbols and their meanings are the same as those in FIG. 3.

After the transmitting computer sends the destination address AD, the receiving computer immediately responds by transmitting on the data line in synchronization with the response tag signal whether or not its own station is in a state where it can accept data. When the transmitting side computer sees this response and determines that the data can be received, it sets the data tag line to 'L' and sends the data to the data line.Also, if the receiving side determines that it cannot receive the data, it sends the data to the data line in Figure 4. , the bus exclusive tank is immediately abandoned as shown by the dotted line.The next transmission timing is
The same operation can be performed again when the receiving side becomes able to receive data again. Since the exclusive bus is released during this time, it becomes possible to transfer data between different computers using the common bus.

As shown in E and E, by first checking the status of the receiving computer before starting the data transfer, it is possible to eliminate unnecessary data transfer and increase the utilization rate of the common bus 2. .

[Brief explanation of drawings]

Fig. 1 is a block system diagram for explaining a conventional data transfer system, Fig. 2 is a block system diagram of an embodiment of the data bus control system according to the present invention, and Fig. 3 is a data bus control system according to the present invention. FIG. 4 is an example of a time chart for explaining data transfer according to another embodiment of the data bus control method according to the present invention. 2...Common bus, 3...-Clock generation circuit, A2, B2, 02...
- Computer, D2... Bus control computer. Agent Makoto Kuzuno - Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1, Indication of case Relationship to patent application No. 56-146860 Patent applicant representative Hitoshi Katayama Department 4, Address of agent Chiyoda-ku, Tokyo Marunouchi 2-2-3 No. 5, Detailed description of the invention column 6 of the specification subject to amendment, Contents of the amendment (1) On page 11, line 12 of the specification, after “Until return”, “Others” should be added. The calculator inserts ".

Claims (2)

[Claims] (1) In a data bus control system that is equipped with a plurality of computers and a common bus that connects these computers in a dendritic manner, and is controlled so that data is transferred between the computers via the common path, one location on the common bus is provided. A first clock signal that includes a common path number and is used to synchronize operations related to all data transfer operations, and a second clock signal that is included in the common path and is the frequency of the first clock signal divided by N. The common path includes at least two different clock lines, a data line for performing multiple data transfers, and a clock generation circuit that generates a clock signal, and the common path includes at least two different clock lines, a data line for performing multiple data transfers, and a clock generation circuit for detecting when a computer has acquired exclusive rights to the common path. When transmission data is generated, the computers connected to the common path are equipped with one dedicated bus line as shown in FIG. When a predetermined number of counts for each computer is counted by a first clock signal, the path exclusive line is significantly driven, and the destination optical computer address information and transmission data are output to the data line; By providing a function that restores the path dedicated line to its original state when data transfer is completed, and a function that imports data to the internal memory when it detects data with the own address information added above on the data line, multiple computers can share a common path. A data bus control method characterized in that data can be transferred to each other without simultaneously monopolizing the bus. (2) In a data bus control system that includes a plurality of computers and a common path that connects these computers in a dendritic manner, data is transferred between the computers via the common path. The first bus is included in the common bus and is used to synchronize operations related to all data transfer operations.
a clock signal, and a clock generation circuit that is included in the common path and generates a second clock signal obtained by dividing the frequency of the first clock signal by N, and the common path includes at least two different clock signals. In addition to the line, it is equipped with a data line for carrying out multiple data transfers, and one path exclusive line that indicates that the computer has acquired exclusive rights to the common path,
When each of the computers connected to the common path generates transmission data, if the common path is not exclusively used, each computer receives a predetermined separate count number for each computer based on the change point of the second clock signal. is counted by the first clock signal, the path dedicated line is significantly driven, and after outputting the destination optical computer address information to the data line, the receiving side receives the response information from the receiving computer. If it is possible to accept the data, then output the transmission data to the above data line, and when the data transfer is completed, return the above path dedicated line to its original state. If the receiving side cannot accept the data, immediately return the bus dedicated line to its original state. The function is to output the above response information to the data line when it detects its own address information on the data line, and if it is possible to receive data, it subsequently captures the data sent from the sending computer into the internal memory. By providing this, multiple computers can transfer data between each other without monopolizing the common path at the same time, and a high common bus utilization rate can be obtained by sending only large amounts of valid data to the common path. A data bus control method characterized by: