JPS5841570B2 - Jikiki Rokusai Seisouchi - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a magnetic recording and reproducing device configured to electrically perform various operations (normal forwarding, fast forwarding, rewinding, etc.) using command switches such as microswitches and keyboard switches. be.

Conventionally, in this type of magnetic recording/reproducing device, the operations range from fast forwarding (hereinafter referred to as F, F) or rewinding (hereinafter referred to as REW) to normal forwarding (hereinafter referred to as PLAY) or stop (hereinafter referred to as PLAY).
When switching to the 5TOP (hereinafter referred to as 5TOP) operation, a method is used in which the motor on the supply or winding side is stopped while it is rotating, and then the motor is brought to a PLAY or 5TOP state.

However, in the conventional method, the brake is applied while the motor is rotating, which places an excessive burden on the brake mechanism and forces the brake mechanism to slow down, which applies tensile force to the magnetic tape, causing damage to the magnetic tape. There was a risk that the tape would stretch.

To prevent this, when switching from F, F or REW operation to PLAY feed or 5TOP operation,
If it is in the state, it is switched once to the FF state, and if it is in the REW state, it is switched to the FF state once, and a voltage is applied to the motor to apply rotational force in the opposite direction, the motor is decelerated, and the rotation of the reel is stopped. The user must then perform the desired operation such as PLAY or 5TOP, which is extremely difficult and troublesome for the user, and there is a risk of damaging the magnetic tape due to incorrect operation. mosquito.

The present invention eliminates the drawbacks as described above, and when switching from FF or REW operation to PLAY or 5TOP operation, if it is in FF state, it is changed to FF state once,
If it is in the REW state, it will automatically switch to the FF state, decelerate the rotation of the motor, change the running direction of the magnetic tape, and at the same time set the desired state such as PLAY or 5TOP, thereby preventing damage to the magnetic tape. It is an object of the present invention to provide a magnetic recording/reproducing device which can prevent this problem and also has a simple brake mechanism.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The figure is an electric circuit diagram showing an embodiment of the magnetic recording/reproducing device according to the present invention, and 1, 2, and 3 are REW, respectively.

For each command switch of FF and 5TOP, each switch 1,
2. One end of 3 is grounded and switches 1, 2, 3
When pressed, the output sides of switches 1, 2, and 3 are also grounded,
It is configured so that a low level signal (hereinafter referred to as a low signal) appears.

Fl is a first memory circuit that is set when the switch 1 is opened and an L signal appears at the output terminal of the switch 1, and F2 is a first memory circuit that is set when the switch 2 is closed and an L signal appears at the output terminal of the switch 2. The second memory circuit F3 is set when the first memory circuit F1 is set, and the third memory circuit F3 is set when the L signal is supplied from the Q output terminal d of the first memory circuit F1. The memory circuit F4 is a fourth memory circuit that is set when the second memory circuit F2 is set and an L signal is supplied from the Q output terminal d of the second memory circuit F2, and each of these memory circuits F1 ~F4 is constituted by a flip-flop circuit based on a NAND gate.

When an L signal is supplied to the set input terminal a of each of these memory circuits F, ~F4, a high level signal (hereinafter referred to as an H signal) is supplied to the Q output terminal C, and an L signal is supplied to the Q output terminal d.
The configuration is such that when an L signal is supplied to the reset input terminal, an L signal is output to the Q output terminal C, and an H signal is output to the Q output terminal d.

D1 to D4 are the memory circuits F1. This is a diode that is a memory reset element that resets each F2, and when the REW command switch 1 is turned on, the two contacts of the switch are closed, and when the L signal is supplied, F2 is reset via the diode D1. When the FF command switch 2 is turned on, the contacts of the switch 2 are closed, and when the L signal is supplied, Fl is supplied through the diode D2, and when the 5TOP command switch 3 is turned on, the two contacts of the switch are closed and the L signal is supplied. When supplied, diode D3. F, , and F2 are connected through D, so that they can be reset, respectively.

G1 is a first gate circuit constituted by a NAND gate, and this gate circuit G1 is set to the first memory circuit F, and an H signal is supplied from the d output terminal of the first memory circuit F1, and the third This is for supplying an L signal to one input terminal of the second gate circuit G2 only when the memory circuit F3 is set and an H signal is supplied from the C output terminal of the third memory circuit F3. The second gate circuit G2 is supplied with an L signal from the first gate circuit G1, or the second memory circuit F2 is set and the second memory circuit F2
When an L signal is supplied from the d output terminal to the other input terminal, the output becomes H, and a signal for driving the FFJ drive circuit 10 is output.

In G3, the second memory circuit F2 is reset and the tI signal is supplied from the d output terminal of the second memory circuit F2, and the fourth
The fourth memory circuit F4 is set and the fourth memory circuit F4 is set to C of the fourth memory circuit F4.
This is for supplying the L signal to one input of the fourth gate circuit G4 only when the H signal is supplied from the output terminal, and the fourth gate circuit G4 receives the L signal from the third gate circuit G3. or when the first memory circuit F1 is set and the L signal is supplied from the d output terminal of the first memory circuit F1 to the other input terminal, the output becomes H and RE
This is for outputting a signal for driving the W drive circuit 11.

These gate circuits 02 to G4 are also connected to the first gate circuits 02 to G4.
Like the gate circuit G1, both are constructed of NAND gates.

4 is a switch circuit which detects that the running direction of the tape has changed or that the running of the tape has stopped, and switches the third and fourth storage circuits F3. This is for supplying an L signal to the reset terminal of F.

5 to 9 are pull-up resistors, and the first and second memory circuits F1
．． F2's a and b input terminals, or the third and fourth memory circuits F3. This is for biasing each input terminal to a high level when the b input terminal of F is not grounded.

10B supplies power to the NAND gate, or resistor 5
This is a power supply source for providing a bias according to ~9.

Next, the operation of the above configuration will be explained in detail with reference to the circuit diagram shown in the figure.

First, when in the REW state, automatically switch to the FF state and then 5TO
The case of setting the state to P will be explained.

If the REW command switch 1 is now in the on state, an L signal is applied to the set input terminal a of the first memory circuit F1, and an L signal appears at the d output terminal of the first memory circuit F1.

Therefore, the output of the fourth gate circuit G4 becomes an H signal, and the REW drive circuit 11 is driven.

In this case, the third memory circuit F3 is set depending on the L signal at the d output terminal of the first memory circuit F1, and the H signal appears at the C output terminal of the third memory circuit F3. .

If the 5TOP command switch 3 is now pressed in this state, the first memory circuit F1 is reset by the diode D3, and an H signal appears from the d output terminal of the first memory circuit F1, which causes the first gate circuit G, supplied to

On the other hand, since the H signal continues to appear at the C output terminal of the memory circuit F3 of the third option, the L signal is supplied from the first gate circuit G1 to the second gate circuit G2, and the output of the second gate circuit G2 becomes H. As a result, the FF drive circuit 10 is driven.

At this time, both inputs of the fourth gate circuit G4 are H signals, and R
The EW drive circuit 11 is not driven.

As described above, when the state changes from <REW to FF, the tape speed gradually slows down, and the tape travels in the opposite direction or approaches a stop, an L signal appears from the switch circuit 4, and this is the third,
Fourth memory circuit F3. The third and fourth memory circuits F3 . F4 is reset and returns to its original state, entering the 5TOP state.

It is clear that when the FF command switch 1 is pressed from REW, the FF state will naturally be entered.

Also, at this time, when the tape running direction changes from the REW state to the FF state, a reset signal is sent from the switch circuit 4 to the third and fourth storage circuits F3. F4, and the third and fourth memory circuits F3. F4 will be reset once.

Next, when in FF state, once automatically switch to REW state, 5TO
The case of setting the state to P will be explained.

If the FF command switch 2 is now on and the L signal is applied to the set input terminal a of the second memory circuit F2, the second memory circuit F2 is set, and the second memory circuit F2 An L signal appears at the d output terminal of.

Therefore, the output of the second gate circuit G2 is an H signal, and the FF drive circuit 10 is driven.

At this time, the fourth memory circuit F4 is set by the L signal appearing at the d output terminal of the second memory circuit F2, and the H signal appears at the C output terminal of the fourth memory circuit F4. .

Now, when the 5TOP command switch 3 is pressed in this state, the second memory circuit F2 is reset through the diode D4, and an H signal appears from the d output terminal of the second memory circuit F2, which is supplied to the third gate circuit G3. be done.

On the other hand, at this time, since an H signal appears at the C output terminal of the fourth memory circuit F4, an L signal appears from the third gate circuit G3, which is supplied to the fourth gate circuit G4.

Therefore, the output of the fourth gate circuit G4 becomes an H signal, and the REW drive circuit 11 is driven.

At this time, the H signal appears at both input terminals of the second gate circuit G2, and the FF drive circuit 10 is not driven.

As described above, the FF state changes to the REW state, the tape speed gradually slows down, and when the tape travels in the opposite direction or approaches a stop, an L signal appears from the switch circuit 4, which is used to store the third and fourth memories. Circuit F3. Since the signals are supplied to the b input terminals of F4, the third and fourth memory circuits F3. F
4 is reset, returns to the original state, and enters the 5TOP state.

Incidentally, when the REW command switch 2 is pressed from the FF state, the REW state is of course maintained.

However, also at this time, when the tape running direction changes from the REW state to the FF state, a reset signal appears from the switch circuit 4, and this is sent to the third and fourth storage circuits F3. F4, and the third and fourth memory circuits F3. F is reset once.

In this way, according to the above embodiment, the third and fourth memory circuits F
3. The set signal for F4 is sent to the first and second storage circuits F
1. REW is supplied while F2 is set.
state, the FF state, and at the start, the switch circuit 4 is in a state of supplying an L signal, and the third and fourth memory circuits F3.
It has the advantage that even if F4 is reset, it will be set immediately and accurately.

In addition, in the embodiment, only the case where a command is given to switch from the REW state or the FF state to the 5TOP state is explained, and the figure only shows that part, but the PLAY command switch and the fact that the PLAY command switch is pressed are explained. A PLAY memory circuit is provided to store the data, and when the PLAY command switch is pressed, the first and second memory circuits F1. If a diode is provided to reset F2, and a gate circuit is provided so that the PLAY state is set when the PLAY memory circuit is set, when the PLAY command switch is pressed from the REW state or FF state, the FF state is temporarily changed to the REW state. In a state of
It is also possible to configure the device to enter the PLAY state at the same time as the tape running direction changes.

As is clear from the examples above, according to the present invention, REW
If you press the PLAY or 5TOP command switch from the FF state, you can automatically and accurately switch to the FF state or REW state, thereby decelerating the rotation of the motor and changing the running direction of the magnetic tape. or when the speed approaches zero, P
The desired state of LAY or 5TOP can be set, and therefore damage to the magnetic tape can be prevented as much as possible.

Therefore, according to the present invention, the brakes can be activated when the rotational force of the motor becomes almost zero, and the brake mechanism can be simplified. It has advantages.

BRIEF DESCRIPTION OF THE DRAWINGS The figure is an electric circuit diagram of an embodiment of the magnetic recording/reproducing apparatus of the present invention. F1-F4... Memory circuit, 01-G4...
...Gate circuit, D1-D4...Diode,
1 to 3...Operation command switch, 4...
Reset circuit, 5 to 9...Resistance.

Claims (1)

[Claims] 1. First and second memory circuits that are set respectively corresponding to the respective command switches when the rewind and fast forward command switches are turned on, and the first and second memory circuits are set. At this time, the third and fourth memory circuits are set corresponding to each memory circuit depending on the respective outputs, the first memory circuit is reset, and the third memory circuit is set. a first gate circuit for detecting, and a second gate for supplying a signal to drive the fast forward drive circuit when the first gate circuit detects the above condition or when the second storage circuit is set. a third gate circuit that detects a state in which the second memory circuit is reset and the fourth memory circuit is set; and when the third gate circuit detects the above state, or A fourth gate supplies a signal to drive the rewind drive circuit when the first storage circuit is set, and a fourth gate detects when the running direction of the magnetic tape changes or the tape speed slows down. 3. A magnetic recording and reproducing device comprising a reset means for resetting a fourth storage circuit.