JPS5831570A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device in which elements are isolated without decreasing the performance of the elements by providing an insulating layer containing charge for depleting the other conductive type impurity region of low density on the surface of an element isolating region. CONSTITUTION:An isolated p type region 28 and a thick insulating film 29 formed on the surface of the region 28 are formed. The boundary region of the element of the isolating region is formed particularly with a p<+> type region 30 of high density, and surrounds the element. In the film 29, positive ions of silicon or argon are implanted to include the positive charge therein, thereby completely depleting a p- type region 28 directly under it. In this manner, in the SOS structure of this embodiment, the isolation between the elements is complete, and no abnormality in the characteristics occur due to the improper gate withstand voltage and parasitic transistor. Since high temperature and long time heat treatment is not necessary, the leakage current between the source and the drain is not increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which elements are formed in a semiconductor layer provided on an insulating substrate.

A technique for forming a semiconductor single crystal thin film on an insulating substrate and forming an element thereon is, for example, gO8 (5iliconOn).
8apphire) technology has been put into practical use and is attracting attention.

A conventional device using such technology will be explained with reference to the drawings.

is1 Figure ta) is a # side view of the conventional device, and Figure 1 (
b) shows a 1llr plane view along the person-λ line. Two MOB@N channel transistor elements T1.T are formed on the sapphire substrate 1.
1. N-type impurity #IIJvs region 3. is added to the OJIIm grown P-type silicon single crystal film 2 as source and drain regions.
4 is formed, and a channel region 5 between the source and drain is formed.
A gate oxide film 6 and a gate electrode 7 are provided thereon, resulting in a nine-structure structure.

These two transistors T1 and T2 are made of silicon 4
By spatially separating the L crystals 12, elements are separated. However, if such a structure is adopted, the gate electrode 7, as indicated by the eleventh peak), will descend onto the insulating film 1 using the @ plane of the silicon single crystal film 2, and then be interconnected with other parts. However, since it is difficult to form an oxide film on the 111 plane of this single crystal -2, the gate breakdown voltage between the gate electrode and the P shadow region of the silicon crystal film 2 tends to be low in this area. . In addition, there is also the drawback that an extra channel is generated on this side surface, forming a parasitic rios transistor and causing abnormal current-voltage characteristics.

Furthermore, a structure as shown in FIG. 2 has also been conventionally used. A P-type silicon single crystal film 12 is formed on the sapphire base 1 [11]. This P-type single crystal film 12 has N-type impurity**
Area 13.11>1 is formed as the source/drain region of the MOS transistor. Further, a gate oxide film 16 is formed on the channel region 15 between the source and drain.
is formed, and a gate electrode 17 is formed on the oxide film 16. Two adjacent MO8s with such a structure
Transistors T□1 and T11 are separated by an Smu02 film 18.

Although such a structure does not have the drawbacks of the conventional example described above, it does have other drawbacks such as linearity.

That is, this isolation film 18 is formed by a thermal oxidation method, and at this time a long-time high-temperature heat treatment step is performed. However, this heat treatment often results in an increase in leakage current between the source and the drain, resulting in a decrease in device performance.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of conventional devices and to provide a semiconductor device in which elements are formed separately without deteriorating the performance of the elements.

The invention will now be described. FIGS. 3(a) and 3(b) are
FIG. 2 is a cross-sectional view and a partial plan view of one embodiment.

Low # degree P type silicon single crystal film 2 on sapphire substrate 21
2 is formed by a vapor phase growth method, and two MO8 type transistors T2.2 are formed on this phosphor crystal film. .

T2□ is formed. The element forming portion of this single crystal film 22 consists of a high AIf N-type diffusion zone 23, 24 in which phosphorus is diffused and which becomes the source and drain of the MOS transistor, and a channel region 25. On this channel region 25, 810□ gate oxide is formed. A probe 26 and an aluminum gate electrode 27 are formed thereon. The isolation region between this element and the adjacent element is the same low concentration P' cedar silicon cylindrical lil! It is formed of 22.

The isolation region consists of a P-shadow region 28 and a thick insulating film 29 formed on its surface. Further, in this outer region, a particularly high concentration p+m head region 3o is formed in the boundary region with the element, which surrounds the element. Further, positive ions such as silicon or argon are implanted into the insulating film 29 to contain a positive charge, so that the p-m* impurity 28 directly below the insulating film 29 is completely depleted.

In general, in the case of a two-layer structure consisting of an insulating film and a semiconductor layer, the charge density Nox (,/sf ) contained in the insulating film near the interface between the insulating film and the semiconductor layer and the impurity concentration C8 (/sf ) below it
The depth dl,1] of the depletion t11 generated in the semiconductor layer d) has the relationship N=dXC8. For example, x charge density in the insulating film It 5 X 10”/d, P-1
[Acceptor of area 28 l1lf 5 X 10”/-
If this P-m region 28 has a thickness of 1 mm or less, it can be completely depleted.

The structure when the P-type separation region is not depleted is as follows:
Since the silicon layer remains in the 1111 region, there is a risk that the original advantage of the SO8 structure, which is that there are fewer floating interconnections and that high-speed operation is possible, will be impaired. However, in this embodiment, since the silicon layer 22 is completely depleted, the capacitance between the wiring and the substrate is divided by the insulating layer and the depletion layer insulating substrate, and does not substantially increase. Another problem with such a structure (J) is that the surface of the silicon layer 22 of the wiring F may be reversed, resulting in poor element isolation.

In this embodiment, since the high concentration P+ type region 30 surrounds the device, no channel is formed between the devices.The P type region 30 of the channel stopper reaches the surface of the sapphire substrate 21. It is not necessary, and only the surface portion of the silicon single crystal film 22 is sufficient. In this way, in the 808 iIf structure of this embodiment, not only is the isolation between elements perfect, but the gate breakdown voltage is There will be no defects or characteristic abnormalities due to parasitic transistors. High temperature again.

1. There is no need for long-term heat treatment, so there is no risk of an increase in leakage between the source and drain.1. Moreover, according to the present invention, it is possible to provide a semiconductor device LIT in which element separation can be performed completely without deteriorating the performance of the element. Note that the positive ions implanted into the insulating film on the surface of the silicon 1- region for 1 minute to form a depletion layer are not limited to silicon or argon, but may be other positive ions.1. Alternatively, impurities may be added to the insulating film, or structural defects may be generated. In this example, N-channel M
OS) transistor, but it goes without saying that it can also be applied to a P channel (a CMO8 structure is also possible).

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional semiconductor device.
b) is a sectional view taken along line A-A in Fig. 1 (13), Fig. 2 is a sectional view of a conventional semiconductor device, and Fig. 3 (a), (b)
) are a cross-sectional view and a plan view of a semiconductor device of the present invention. 21...Insulating substrate 23...Source region 24...Drain region 22...Channel region 28...Last son isolated P-type region 9...Insulating film agent Patent attorney Noriyuki Chika ( 1 other person) Envy 7

Claims (1)

[Claims] A semiconductor layer comprising an insulating base and a plurality of element regions and an element isolation region formed on the base, the element region comprising a plurality of impurity regions of one conductivity type and a channel region sandwiched therebetween, The element isolation region is mainly composed of a low concentration impurity region of another conductivity type, and a high concentration impurity region of another conductivity type is formed at the boundary with the m-th generation element region. A semiconductor device characterized in that the semiconductor device further comprises an insulating layer containing charges such that the low concentration impurity region of another conductivity type can be made into a depletion layer.