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JPS5831553A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5831553A
JPS5831553A JP56129522A JP12952281A JPS5831553A JP S5831553 A JPS5831553 A JP S5831553A JP 56129522 A JP56129522 A JP 56129522A JP 12952281 A JP12952281 A JP 12952281A JP S5831553 A JPS5831553 A JP S5831553A
Authority
JP
Japan
Prior art keywords
film
single crystal
sio2
forming
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56129522A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP56129522A priority Critical patent/JPS5831553A/en
Publication of JPS5831553A publication Critical patent/JPS5831553A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To accelerate the operation of a semiconductor device inexpensively by forming an SiO2 film partly opened with a window on the surface of a single crystal Si substrate, forming a single crystal Si film on the surface and forming an SiO2 film at least partly thermally oxidized in contact with a primary SiO2 film. CONSTITUTION:In order to form an Si film 5, an Si film in a window is formed by high temperature CVD in a single crystal Si film, and an Si film on an SiO2 is formed in a polycrystalline Si film. The film 5 is thermally oxidized until the second dielectric isolation region 8 is contacted with a primary SiO2 film 4. Thereafter, the film 5 is instantaneously melted by laser annealing, infrared ray or Xe lamp annealing from the surface to be converted into single crystal, thereby forming a single crystal Si film, an N type well 9 or a P type well 10 is formed by ion implantation in the windows of the Si film and the Si substrate, a source and drain region is formed by the ordinary MOS FET manufacture, a hole is then opened, and aluminum wire is deposited.

Description

【発明の詳細な説明】 本発明は半導体装着とその製造方法に係り、特に薄膜半
導体装置の誘電体分離法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor mounting and its manufacturing method, and more particularly to a dielectric isolation method for thin film semiconductor devices.

従来、81半導体装置は単結晶81基板上に半導体装着
が形成されるため素子間が誘電体で完全罠分離されてい
ないため、高速性能が得られないという欠点があった。
Conventionally, the 81 semiconductor device had a drawback in that high-speed performance could not be obtained because the semiconductor mounting was formed on a single crystal 81 substrate and the elements were not completely isolated by a dielectric material.

上記欠点をなくするために完全に素子間t−銹電体分離
した半導体am、=して80B(シリコン・オン・サフ
ァイヤ)tCよる半導体装置が製作されているがサファ
イヤ基板のコスト高という欠点があり、一般的に用いら
れていない。
In order to eliminate the above-mentioned drawbacks, a semiconductor device using 80B (silicon-on-sapphire) tC, which is a semiconductor am with complete t-electric isolation between elements, has been manufactured, but it has the disadvantage of high cost of the sapphire substrate. Yes, but not commonly used.

しかるに、最近、ラテプル・エピタキシャル技術により
、部分的に窓開けさfiた81基板上の810、膜上に
も単結晶5illt育成する技術が開発された。
However, recently, a technique has been developed for growing a single crystal 5 illt on a partially windowed 81 substrate and also on a film using the late pull epitaxial technique.

本発明はかかる81基板上の部分的に窓開けさfL7′
e810.膜上への81膜の形成技術を応用して、前記
従来技術の欠点tなくした、低コストで高速の半導体装
#1を提供する事を目的とし、そのための誘電体分離法
1に提供するものである。
The present invention provides a partially windowed fL7' on such an 81 substrate.
e810. The purpose of this invention is to provide a low-cost, high-speed semiconductor device #1 that eliminates the disadvantages of the prior art by applying the 81 film formation technology on a film, and provides a dielectric isolation method 1 for that purpose. It is something.

本発明の目的を達する基本構成は、単結晶81基板表面
には部分的に窓開けされた、FliOlMが形成され、
該窓開けさfi7csiO,膜を含む基板表面Vcは単
結晶81膜が形成さn1前配窓開けζnたd j O,
膜上の単結晶B111@の少なくとも一部倉熱酸化によ
る810m膜となし、下地日10.膜と接して成ること
t41!命とする。
The basic configuration that achieves the object of the present invention is that FliOlM with a partially opened window is formed on the surface of the single crystal 81 substrate.
The window opening is fi7csiO, and the substrate surface Vc containing the film is formed with a single crystal 81 film.
At least a portion of the single crystal B111@ on the film was formed into an 810m film by oxidation, and the base date was 10. Being in contact with the membrane t41! Make it your life.

以下、実施例に沿って本発明を具体的に説明する。The present invention will be specifically described below with reference to Examples.

m1図は本発明の一実施例を不−rc−MO8ICの製
造工程である。
Figure m1 shows the manufacturing process of a non-rc-MO8IC according to an embodiment of the present invention.

単結晶81ウェーハ1上には薄い熱生成S10゜膜2お
よびflVDKよる81mNa嘆3を形成し、窓開は部
のみのs i、 N、 tillをホト(P、R,)・
エツチングにより残し、81.N、膜を酸化マスクとし
て、第1の誘電体弁4810.膜4ヶ比較的摩く形成し
、薄い5102膜1及びS i、 N、膜2等を除去し
、窓部の下池単結晶81基板を露出させる。次でCVD
法によりS1膜5t−形成する。この場合、日IH4の
熱分解VCよるCVD法によりS1腓5を杉1.し「る
のであるが、高幅(900℃〜1200℃ンCVDでは
窓部の81膜は単結晶S1嘆に、5j01上の81膜は
多結晶B1嚇となり、比較的低温(500℃〜800℃
)CVI:でげ1パ都も810゜上も#に多結晶B1嗅
となり、いず11の生・t’t、法でも良い。この場合
は前者の生成法によった。次に、薄イsio、%1i(
S、CVDKj6S1iN+’NZ k杉IJ7し、ホ
トエツチングによりs 1115の下地dio1813
4の上の誘電体分離すべき部分の513N、膜Z全除去
して、n 5isN4膜7 ff酸化マスクとして81
膜5を熱酸化して第2の誘電体分陰領域8くcト地Si
n、[4に接するまで酸化形成する。その後、レーザー
・アニールあるいは赤外線アニール、あるいσXsラン
プ・アニール等にエリ前j1sim5會表面から瞬時融
解して単結晶化する、いわゆるラテラル・エピタキシャ
ル処理により単結晶61膜となし、イオン伽込みに↓す
Sil漠及び#31基板の窓@tNウェル9あるいiP
ウェル10を形成し、以t&o通常のMOS  FET
の表作法にエリゲート酸化幌11、ゲート多結晶811
2、ソース・ドレイ/1IJI域15等を形成してCV
DKよる810.[14i形戎し、コンタクト穴開は後
、M蒸層配#15を施丁。
On a single crystal 81 wafer 1, a thin thermally generated S10° film 2 and an 81 mNa film 3 made of flVDK were formed, and the window openings were made by photo(P, R,), N, and TILL.
left by etching, 81. N, using the membrane as an oxidation mask, the first dielectric valve 4810. Four films are relatively polished, and the thin 5102 film 1, Si, N, film 2, etc. are removed to expose the Shimoike single crystal 81 substrate in the window portion. CVD next
An S1 film 5t is formed by the method. In this case, cedar 1. However, in high width (900°C to 1200°C) CVD, the 81 film on the window part becomes monocrystalline S1, and the 81 film on 5j01 becomes polycrystalline B1, and at relatively low temperature (500°C to 800°C) ℃
) CVI: Dege 1 part and 810 degrees above become polycrystalline B1 smell, and Izu 11's raw/t't, law is also good. In this case, the former generation method was used. Next, thin isio,%1i(
S, CVDKj6S1iN+'NZ k cedar IJ7 and photo-etched s1115 base dio1813
Completely remove 513N and film Z of the part to be dielectrically separated above 4, and use 81 as n5isN4 film 7ff oxidation mask.
The film 5 is thermally oxidized to form a second dielectric shaded region 8.
Oxide is formed until it touches n, [4. After that, it is formed into a single crystal 61 film by laser annealing, infrared annealing, or σXs lamp annealing, etc., which instantaneously melts the j1sim5 surface in front of the edge and turns it into a single crystal, resulting in a single crystal 61 film.↓ Sil and #31 board window @tN well 9 or iP
Form well 10, and then t&o ordinary MOS FET
Elli gate oxide hood 11, gate polycrystalline 811 for the surface method
2. Form source drain/1IJI area 15 etc. and CV
810 by DK. [After cutting out the 14i shape and drilling the contact hole, apply the M vapor layer #15.

この様にして製作されたMOS、FICTU、  ソー
ス・ドレイ/等の拡散領域が誘電体膜上及び誘電体弁S
−等でほぼ完全に分離さfl友状態となり配線の電気容
量が小となり、高速化か引れると共に、基板にサファイ
ヤ等の高価な)+1板を用いる会費はなく、通常の81
ウエーノ・で良く、低コスト化もIすれる効果がある。
The diffusion regions of the MOS, FICTU, source/dray/etc. manufactured in this way are on the dielectric film and on the dielectric valve S.
-, etc., it becomes almost completely separated, the electric capacitance of the wiring becomes small, the speed increases, and there is no need to use an expensive +1 board such as sapphire for the board, and the normal 81
Ueno® is sufficient and has the effect of lowering costs.

【図面の簡単な説明】[Brief explanation of drawings]

jJ4を図(a−g)は本発明に!@る誘電体分離a 
−vos’工0の製造方法を示す工程毎の従断i10図
である。 1・・・81;Iii板、2.6・・・slo、膜、5
.7・・・81、N番膜、4・・・講1誘璽体分暑5t
otll!x  5・・・日IM18・・・第2a電体
分離810.、?・・・Nウェル、10・・・Pウェル
、11・・・ゲート810x Pa512−・−ゲート
多結晶i11.13−・・拡散S i m、14・・C
VD−8i○、膜、+5・・M配−0以   上 出願人 株式会社譚訪梢工舎 代理人 弁理士電上  務 第1N 第1図
Figures (a-g) show jJ4 according to the present invention! @ dielectric separation a
-Vos' Process 0 is a cross-sectional diagram for each process showing the manufacturing method. 1...81; III plate, 2.6... slo, membrane, 5
.. 7...81, Nth film, 4...1st layer heat 5t
otll! x 5...day IM18...2nd a electric body separation 810. ,? ...N well, 10...P well, 11...gate 810x Pa512--gate polycrystalline i11.13-...diffusion S i m, 14...C
VD-8i○, membrane, +5...M-0 or more Applicant: Tanbozukosha Co., Ltd. Agent Patent Attorney Denjou No. 1N Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)単結晶81基板表面には部分的に窓開けされた8
10鵞膜が形成され、該窓開けされた8102膜を含む
基板表面には単結晶81膜が形成され、前記S開けさn
k810.膜上の単結晶B1膜の少なくとも一部を熱酸
化による8101膜となし、下地8103膜と接して成
ることt特命とする半導体装置。 12)  単結晶81基板表面Kl−J部分的に窓開け
され7t810.膜が形成され、該窓開けされた810
゜膜を含む基板表面には単結晶S1膜が形成され、前記
窓開けさnたB101膜上の単結晶81膜の少なくとも
一部を熱酸化による810[膜となし、下地810.膜
と接して成ることを%像とする半導体装置の製造方法。
(1) Single crystal 81 The surface of the substrate has a partially opened window 8
A single crystal film 81 is formed on the surface of the substrate including the window-opened 8102 film.
k810. A semiconductor device in which at least a part of the single crystal B1 film on the film is made into an 8101 film by thermal oxidation and is in contact with an underlying 8103 film. 12) Single crystal 81 substrate surface Kl-J partially opened 7t810. The membrane is formed and the window is opened 810
A single-crystal S1 film is formed on the surface of the substrate containing the film, and at least a part of the single-crystal S1 film on the window-opened B101 film is thermally oxidized to form an 810 film and an underlying 810 film. A method for manufacturing a semiconductor device that focuses on the formation of a semiconductor device in contact with a film.
JP56129522A 1981-08-18 1981-08-18 Semiconductor device and manufacture thereof Pending JPS5831553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56129522A JPS5831553A (en) 1981-08-18 1981-08-18 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56129522A JPS5831553A (en) 1981-08-18 1981-08-18 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5831553A true JPS5831553A (en) 1983-02-24

Family

ID=15011579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56129522A Pending JPS5831553A (en) 1981-08-18 1981-08-18 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5831553A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679595A (en) * 1994-10-11 1997-10-21 Mosel Vitelic, Inc. Self-registered capacitor bottom plate-local interconnect scheme for DRAM
US5679588A (en) * 1995-10-05 1997-10-21 Integrated Device Technology, Inc. Method for fabricating P-wells and N-wells having optimized field and active regions

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5673697A (en) * 1979-11-21 1981-06-18 Hitachi Ltd Manufacture of single crystal thin film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5673697A (en) * 1979-11-21 1981-06-18 Hitachi Ltd Manufacture of single crystal thin film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679595A (en) * 1994-10-11 1997-10-21 Mosel Vitelic, Inc. Self-registered capacitor bottom plate-local interconnect scheme for DRAM
US5880496A (en) * 1994-10-11 1999-03-09 Mosel Vitelic, Inc. Semiconductor having self-aligned polysilicon electrode layer
US5679588A (en) * 1995-10-05 1997-10-21 Integrated Device Technology, Inc. Method for fabricating P-wells and N-wells having optimized field and active regions
US5926704A (en) * 1995-10-05 1999-07-20 Integrated Device Technology, Inc. Efficient method for fabricating P-wells and N-wells

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