JPS58220540A - Controlling system of network congestion state - Google Patents

Abstract

PURPOSE:To execute quickly information of generation of a congested state of a low speed receiving memory in a low speed data transmitting and receiving circuit, by always monitoring the congestion of the low speed receiving memory by a high speed receiving buffer memory monitoring circuit, so that it can be informed to a high speed transmitting and receiving circuit in its own way. CONSTITUTION:A high speed receiving buffer memory monitoring circuit 315 in a high speed data transmitting and receiving circuit 310 always monitors a low speed buffer existence circuit 610 in a low speed data transmitting and receiving circuit, and receives a data from a high speed data switching network 400 when a low speed receiving memory 412 is not congested. A data to be sent to a low speed data transmitting and receiving circuit 410 is stored in a high speed receiving buffer memory 311 and a normal receiving response is returned. Thereafter, this data is transferred to the low speed receiving memory 412 in the low speed transmitting and receiving circuit 410. On the other hand, when the low speed receiving memory 412 in the low speed transmitting and receiving circuit 410 is in a congested state, a response of generation of a congested state of the low speed receiving memory is set to LA against the received data.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a network congestion control system for intra-node buffers in a high-speed data exchange network that transmits multiplexed messages.

Prior Art When multiple low-speed data transmitting/receiving circuits exchange data via a high-speed data exchange network that transmits multiplexed messages, conventional nodes have the configuration shown in FIG. 2, and the data shown in FIG. The data was transferred and traffic control was performed using the method shown in Figure 4.

In Figure 1, data 01 is surrounded by flags (F) 02 to identify the preceding and following data, a transmitting node number (8A+) 05 to identify the transmitting node, and a low-speed data transmitting/receiving circuit on the transmitting side. Sending side low speed data transmission/reception circuit number (SA to ) 04 to identify the receiving side node number (DA+) o5 to identify the receiving side low speed data transmission/reception circuit. Transmission/reception deflection path number (DA 06, control field for data serial number management (C1o7,
Information Department (110th, Fe2 Department (Fe2) 09, which performs CRC check on data, and Response Department (LA)
Consists of 10.

In FIG. 2, a demodulation circuit 101 demodulates data sent from a high-speed data exchange network 400 to receive thick 10
Transfer to 4. When the flag detection circuit 106 detects that 7lag 02 is input to the reception shifter 104, the DA comparison circuit 107 checks whether the data is addressed to the own node or not, and if the data is addressed to the own node, the high-speed data transmission/reception circuit 310
and stored in the reception buffer memory 511.

Terminal reception control circuit 411 of low-speed data transmission and reception circuit ago
always issues a data transfer request to the low-speed data receiving circuit 315 when the low-speed receiving memory 412 of the low-speed data transmitting/receiving circuit does not overflow, and transfers the data from the high-speed receiving buffer memory 511 to the low-speed receiving memory 412 (Fig. 4). −■).

When the data transfer is completed, the low-speed reception memory 412 is checked to see if the next data can be received.When the low-speed reception memory 412 is overflowing, no data transfer request is issued to the low-speed data reception circuit 515 (FIG. 4-@).

The terminal transmission control unit 414 also instructs the low-speed data transmission/reception circuit of the other party to transfer data that notifies the communication status, and the terminal transmission control unit 414 transmits data to the low-speed data transmission circuit 314.
, the high-speed transmission buffer memory 312, and the transmission shifter 105 to notify the other node of the traffic status (FIG. 4--).

Figure 4 shows the flow of the conventional network width control system, in which a node receives data destined for itself. ,
・Data is transferred from the low-speed data transmission/reception circuit 1 to receive a data transfer request (Fig. 4-■).

To receive data destined for the own node (Fig. 4-■) There is a data transfer request from the low-speed data transmitting/receiving circuit, so the data is transferred (Fig. 4-○).

The low-speed data transmitting/receiving circuit detects congestion in the low-speed receiving memory (Fig. 4-■), does not issue a data transfer request (Fig. 4-○), and sends data to notify the other node of the occurrence of congestion. (Fig. 4'-〇) shows an example.

Because of the configuration and method described above, if the low-speed reception memory of the low-speed data transmission and reception circuit overflows and a width envy state occurs, the low-speed data transmission and reception circuit itself
When the low-speed data transmitting/receiving circuit detects a congestion state in the low-speed receiving memory without creating a congestion state occurrence notification frame to the other node, the notification to the other party's low-speed data transmitting/receiving circuit is delayed.

Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned conventional problems, and to provide a method for quickly notifying a communication partner node of the congestion status of a low-speed receiving memory in a low-speed data transmitting/receiving circuit. The object of the present invention is to provide an effective network congestion control method.

Conventionally, when a congestion state occurs in the low-speed reception memory in the low-speed transmission/reception circuit, a congestion notification frame is sent to the communication partner.

The present invention focuses on whether it is possible to quickly resolve the congestion state of the low-speed reception memory in the low-speed transmitting/receiving circuit, and by having a high-speed reception buffer memory monitoring circuit constantly monitor the congestion of the low-speed reception memory. This is based on the idea that high-speed transmitting and receiving circuits can independently send notifications.

Embodiments of the Invention Next, embodiments of the invention will be described in detail with reference to the drawings.

FIG. 3 shows the configuration of a node according to an embodiment of the present invention, which transfers the data shown in FIG. 1 and performs control using the method shown in FIG.

The differences between FIG. 5 and FIG. 2 are as follows.

The high speed reception buffer memory 311 is connected to the high speed reception buffer memory*multiple circuit 515, and the high speed reception buffer memory monitoring circuit 515 is connected to the buffer presence/absence display circuit 610 and the LA creation circuit 111.

Further, the buffer presence/absence display circuit 610 is connected to the low-speed reception memory 412.

As a result, when the low-speed reception memory 412 is in a busy state,
Via the buffer presence/absence display circuit 610 and the high-speed reception backup memory monitoring circuit 315, the LA creation circuit 111 is informed that the low-speed reception memory 412 is in a congested state.

The LA creation circuit 111 sets a pattern in which the low-speed reception memory 412 is in the congestion state in the response unit 10 and transmits it to the reception shifter 1.
It is to be transferred to 04.

Next, FIG. 5 shows an example of data transfer according to the present invention.

The high-speed reception buffer memory monitoring circuit @315 in the high-speed data transmission/reception circuit 610 always receives low-speed data.

The low-speed ballast presence/absence circuit 610 in the transmitting/receiving circuit should be monitored (Figure 5-0), when the low-speed receiving memory 412 is not crowded (
FIG. 5-■) is received from the high-speed data exchange network 400.

The data destined for the low-speed data transmitting/receiving circuit 41.0 is stored in the high-speed reception backup memory 311 (FIG. 5-■), and a normal reception response is returned (FIG. 5-■).

Thereafter, the data is transferred to the low-speed reception memory 412 in the low-speed transmission and reception circuit 410 (FIG. 5-■).

On the other hand, when the low-speed reception memory 412 in the low-speed transmission/reception circuit 410 is in the congestion state (Fig. 5--), a low-speed reception memory congestion state occurrence response is set in LA for the received data (Fig. 5--). -@).

Effects of the Invention With the configuration as described above, the present invention has the advantage that notification of the congestion state of the low-speed receiving memory in the low-speed data transmitting/receiving circuit can be promptly performed.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional data format, FIG. 2 is a block diagram of a node in the prior art, and FIG. 3 is a block diagram of a node in an embodiment of the present invention. FIG. 4 is a flowchart of a network control method in the prior art. FIG. 5 is a flowchart of a network congestion control method in an embodiment of the present invention. 01...Data 02...Flag 03
...Sending side code number 04...Sending side low speed data transmission/reception d path number 05...Receiving side node number 06...Receiving side low speed data transmission/reception circuit number 07...
Control field 08...Information section 09...FC8 section 1
0...Response section 100...Node 101...Demodulation circuit 102...Modulation circuit 1o5...In the transmission/reception circuit 04...Reception shifter 105...Transmission shifter 106...Flag detection circuit 107.・
・DA comparison circuit 108...flag creation circuit 109
...SA comparison circuit 110...LA initial setting circuit 111...LA creation circuit 510...High speed data transmission/reception circuit 311...High speed reception buffer memory 612...High speed transmission buffer memory 616...Low speed Data reception 1i circuit 314...Low speed data transmission circuit 615...High speed reception backup memory monitoring circuit 410...
...Low-speed data transmission/reception circuit 411...Terminal reception control circuit 412...Low-speed reception memory 413...Low-speed transmission memory 414...Terminal transmission et al! 6500 per ItIla time...
・Path 610...Low speed buffer shoulderless display circuit 1st port OL O 2 Figure 3rd factor 4ρ0 < 4th country Ise J-do own node'

Claims (1)

[Claims] t In a high-speed data exchange network consisting of a high-speed data transmission path and multiple nodes connected to the high-speed data transmission path, each node has a high-speed data transmission/reception circuit that controls communication with the high-speed data transmission path, and a node accommodating circuit. It consists of a low-speed data transmitting/receiving circuit that controls communication with the terminal below, and the high-speed data transmitting/receiving circuit has a high-speed buffer memory to match the communication speed with the high-speed data transmission line and the processing speed of the low-speed data transmitting/receiving circuit. The low-speed data transmitting/receiving circuit has a low-speed memory necessary for communication with a terminal connected to the low-speed data transmitting/receiving circuit, and the low-speed receiving memory displays whether or not the low-speed receiving memory is in a busy state. A buffer presence/absence display circuit is connected, and the high-speed reception backup memory constantly monitors the low-speed buffer presence/absence display circuit, thereby instantly detecting the occurrence of a congestion state in the low-speed reception memory, and performs processing in the low-speed data transmission/reception circuit. This patented network congestion control method notifies the communication partner node of the occurrence of low-speed memory congestion via a high-speed transmission path using only a high-speed data transmitting/receiving circuit.