JP2000222374A - Load distribution type packet parallel processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent processing from being concentrated on a specific packet processing part in a communication controller in a multi-processor constitution. SOLUTION: The load distribution type packet parallel processor having plural packet processors 31-35 is provided with a load level deciding part for deciding the load level of its own packet processor and a transmission and reception controlling part for operating response processing to a packet processing request according to the load level decided by the load level deciding part. Thus, the transmission and reception controlling part can operate the response processing according to the load level of its own packet processor so that the load can be prevented from being concentrated on the specific packet processor. As for the response processing to be operated by the transmission and reception controlling part, the response processing to the packet processing request is operated according to the load level decided by the load level deciding part equal to a prescribed threshold or more, or a responding time to the packet processing request is changed according to the load level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor communication control device for processing control packets received from one or more communication channels.

[0002]

2. Description of the Related Art In a communication control device for processing a large number of control packets at high speed, a multiprocessor configuration has conventionally been employed in order to increase the processing capability.

FIG. 3 is a block diagram of a base station controller of a mobile phone system applied to one of the conventional communication control devices having a multiprocessor configuration ("Radio base station apparatus for digital automobile / mobile phone system"). , FUJITSU.4
5.2, p112-p116).

[0004] The communication channels 1001 to 100N are connected to opposing devices such as a radio base station and another base station control device via an electronic exchange or the like. Control packets sent from the other device (for connecting each terminal, or
Various control packets for terminating the connection) are stored in a buffer corresponding to the communication channel among the data relay buffers 2001 to 200N of the data relay unit 1 via any communication channel. Bus Interface 2
Monitors the data relay buffers 2001 to 200N of the data relay unit 1 via the I / O bus 4, and when any of the data relay buffers 2001 to 200N detects the reception of the control packet, the shared bus 5 A packet processing request signal is output to the packet processors 31 to 35 via the CPU.

[0005] The transmission / reception control unit 301 of the packet processors 31 to 35 that has received the packet processing request signal has no relation to the amount of packets staying in the reception buffer 302 or the transmission buffer 303 or the processing being executed by the packet processing unit 303. And outputs a packet processing response signal to the bus interface 2. The bus interface 2 that has received the response signal selects the packet processor that has output the packet processing response earliest from among the packet processors that have responded to the packet processing request signal, and gives the packet processing permission to the packet processor.

The transmission / reception control unit 301 given the packet processing permission reads the control packet from the data relay buffer that has received the control packet via the shared bus 5, the bus interface 2, and the I / O bus 4, and receives the control packet. The data is stored in the buffer 302. The packet processing unit 304
The control packet is read from the reception buffer 302, the contents of the control packet are analyzed, and necessary processing is performed.

[0007] In many cases, a new control packet is created based on the processing result, and the control packet is stored in the transmission buffer 303. The transmission / reception control unit 301 reads a control packet from the transmission buffer 303, and transmits the control packet to a corresponding communication channel via the shared bus 5, the bus interface 2, and the I / O bus 4.

When the packet processors 31 to 35 having the multiprocessor structure functioning as described above use the shared resources with other packet processors, the other packet processors cannot use the shared resources in order to maintain consistency of the shared resources. Then use shared resources. That is,
In order for any one of the packet processors 31 to 35 to occupy and use the shared resource, an exclusive flag associated with the shared resource is provided. If the exclusive flag can be acquired, the shared resource can be used, and the exclusive flag can be acquired. Otherwise, an exclusive control method is used such that the use of shared resources is impossible.

For example, a shared memory 6 via a shared bus 5
In the access to the shared data, an exclusive flag is set to restrict the access to the shared data. When it is necessary to access the shared data on the shared memory 6 while processing the control packet, the packet processors 31 to 35 first try to acquire an exclusive flag. Packet processor 3
When the exclusive flag can be acquired, the access to the shared data is possible.
After the access is completed, the exclusive flag is released. When one of the packet processors 31 to 35 acquires the exclusion flag, the other packet processors cannot acquire the exclusion flag, and cannot access the shared data. Thus, the packet processor that cannot access the shared data cannot continue the processing of the packet currently being processed.

However, the control packet is transmitted to the reception buffer 30.
2 is stored in the packet processor 31.
Waiting until .about.35 can acquire the exclusive flag causes a useless idle state in the packet processor. Therefore, the current processing is interrupted, and the next control packet is read from the reception buffer and processed. Then, the interrupted process is restarted when the exclusive flag can be acquired.

[0011]

As described above, when packet processing permission is given to a packet processor which responds to the packet processing request signal output from the packet distribution control unit 21 earliest, each of the packet processors becomes the state of its own packet processor. And control packets are received irrespective of the processing being executed, and the load may be concentrated on a specific packet processor.

For example, the transmission / reception control units 301 of the packet processors 31 to 35 have the same configuration, but there is a high possibility that a slight difference occurs in the response speed due to manufacturing variations. In such a case, there are a packet processor that outputs a packet processing response signal slightly earlier and a packet processor that outputs a packet processing response signal slightly later in the packet processing request signal output by the packet distribution control unit 21. As described above, when a difference in response time of the transmission / reception control unit 301 of the packet processors 31 to 35 occurs, the transmission / reception control unit 3 that tends to respond quickly
01, the frequency of obtaining the packet processing permission from the packet distribution control unit 21 increases, and the frequency of obtaining the packet processing permission of the transmission / reception control unit 301, which tends to respond slowly, decreases.

As a result, there is a problem that many control packets stay in the reception buffer 302 of the packet processor that receives the packets intensively, and a large delay occurs before the packets are processed by the packet processing unit 304. . If a packet processor holding many control packets in such a reception buffer 302 receives more control packets, the processing delay is further increased, so that newly arrived control packets are stored in the control buffer held in the reception buffer 302. It should be distributed to packet processors with a small amount of packets.

Further, if manufacturing variations are small,
Even if the control packets are evenly distributed to the reception buffers 302 of the packet processors 31 to 35, the processing time of the packet processing unit 304 varies depending on the type of the control packets. As a result, many control packets also remain in the reception buffer 302 of the packet processor that has received many control packets with a long processing time,
Similarly, there is a problem that a large delay occurs.

When the control packet receiving capability of a specific opposing device reaches the limit, the transmission speed of control packets from the transmission buffer 303 to the opposing device becomes slow, and the control packets stay in the transmission buffer 303. In such a case,
Since the control packets are transmitted in the order in which they are stored in the transmission buffer 303, a large delay occurs not only in the control packet to the opposite device whose reception capability has reached the limit but also in the transmission of the control packet to another opposite device. There is a problem that. If control packets are received while a large number of control packets are held in the transmission buffer 303, the number of control packets staying in the transmission buffer 304 increases, and the time until the completion of transmission of the control packets further increases. Therefore, newly arrived control packets should be distributed to packet processors in which many control packets do not stay in the transmission buffer 303.

Further, only the amount of control packets staying in the reception buffers 302 and the transmission buffers 303 of the packet processors 31 to 35 does not affect the processing time of the control packets of the packet processors 31 to 35.
That is, the packet processing unit 304
Although the control packet has been read from step 2, the processing is interrupted because access to the shared resource is not possible,
The next control packet may be read and processed. When the number of interrupted processes increases in the packet processing unit 304, there is a problem that a large delay occurs until the processing of the control packet is completed. As described above, when a new control packet is received and processed in a state where many control packets are being interrupted in the packet processing unit 304, the resumption of the interrupted process is delayed or the number of interrupted control packets is reduced. Since the number of control packets increases or the time until the completion of the processing of the control packet becomes longer, the newly arrived control packet should be distributed to a packet processor which does not have a lot of suspended processing.

In some cases, the packet processing unit 304 performs an important and highly urgent process. For example, there are processing for detecting a hardware failure and switching to spare hardware, and processing for periodically checking the consistency of management data on the shared memory 6. If the management data on the shared memory 6 becomes inconsistent, a part of the system cannot operate normally if the inconsistency is left as it is, and as a result, a part of the service operates normally. Can not do.

To cope with this, if an inconsistency is found in the management data on the shared memory 6, the packet processor that has found the inconsistency starts a process for recovering the inconsistency. Such inconsistency recovery processing has high priority and urgency, so even if the packet processor newly receives a control packet, the control packet processing is performed after the processing for inconsistency recovery ends. Therefore, there is a problem that the processing delay of the control packet becomes very large. Therefore, a newly arrived control packet should not be distributed to a packet processor performing such a high priority and urgent processing.

In view of the above points, the present invention distributes the load of the processors in a multiprocessor configuration evenly without being biased to a specific packet processor, and as a result, the processing time of control packets varies greatly. It is an object of the present invention to provide a load distribution type packet parallel processing device which does not cause the problem.

[0020]

The present invention employs the following means to achieve the above object. First, the present invention provides one or more communication channels, a plurality of packet processors for processing control packets received from the communication channel, and a packet distribution for distributing control packets received from the communication channel to the plurality of packet processors. Control unit, when a new control packet arrives at the communication channel, the packet distribution control unit outputs a packet processing request to the plurality of packet processors, and processes the packet processing request to the packet processor that responded to the packet processing request earliest. It is premised on a load-distributed packet parallel processing device that gives permission.

In the above-mentioned load-distributed packet parallel processing apparatus, each of the packet processors is provided with a load level determining unit for determining a load level of its own packet processor, and the packet processor according to the load level determined by the load level determining unit. A transmission / reception control unit that performs a response process to a processing request is provided.

Accordingly, the transmission / reception control unit performs a response process according to the load level of the own packet processor, so that the load does not concentrate on a specific own packet processor.

As the response process of the transmission / reception control unit,
When responding to the packet processing request according to a predetermined threshold of the load level determined by the load level determining unit, or changing the time for responding to the packet processing request according to the load level. The case is conceivable.

Further, when the load level in the load level determining section is determined according to the amount of control packets held in a receiving buffer provided in the packet processor,
When determined according to the amount of control packets held in the transmission buffer, according to the amount of control packets that are being interrupted by the packet processing unit provided in the packet processor,
When determining the load level included in the packet processor, the load level may be determined according to the type of processing in a packet processing unit included in the packet processor.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a block diagram showing the configuration of a load balancing packet parallel processing apparatus according to Embodiment 1 of the present invention, and FIG. It is a block diagram which shows the detail of -35. Hereinafter, the configuration and the operation will be described. First,
This embodiment is characterized in that the transmission / reception control unit outputs a processing response signal based on a load level exceeding a threshold value, so that reference numeral 3011 is used as the reference numeral of the transmission / reception control unit.

The states of the packet processors 31 to 35 are assumed as shown in Table 1 below.

[0027]

[Table 1]

In such a state, the communication channel 100
It is assumed that the control packet has arrived at the data relay unit 1 from 2. The arrived control packet is first stored in the data relay buffer 2002. Next, the packet distribution control unit 21 that monitors the data relay buffers 2001 to 200N in order at a fixed period,
2 that the control packet is stored. Then, it outputs a packet processing request signal to the packet processors 31 to 35 via the shared bus 5.

Upon receiving the packet processing request signal, the transmission / reception control unit 3011 on each of the packet processors 31 to 35 requests the load level determination unit 305 to notify the load level of its own packet processor. The load level determination unit 305 that has received the request determines the load level of its own packet processor by various methods described in the following third to sixth embodiments, and replies to the transmission / reception control unit 3011.

The transmission / reception control unit 3011 that has received the load level of its own packet processor in this way must make sure that the load level does not exceed a predetermined threshold value (here, the threshold value is assumed to be in the load level). For example, a packet processing response signal is output to the packet distribution control unit 21. Since the packet processors 32 to 35 do not exceed the threshold value “during load level” in the state shown in Table 1, the transmission / reception control unit 3011 outputs a packet processing response signal to the packet distribution control unit 21. On the other hand, in the case of the packet processor 31 having a high load level, such as the packet processor 31, the threshold value has exceeded the “medium load level”.
The packet processing response signal is not output to the packet distribution control unit 21. In the above description, the packet processing response signal is output when the threshold value is not exceeded. However, depending on the definition of the threshold value, the packet processing response signal may be output when the threshold value is exceeded. It is possible.

The packet distribution control unit 21 gives a packet processing permission to the packet processor which outputs the packet processing response signal earliest. Packet processors 32-35
Outputs a packet processing response signal, and the packet processor 31 does not output a packet processing response signal. As a result, the packet distribution control unit 21 gives the packet processing permission to one of the packet processors 32 to 35 that has output the packet processing response signal earliest (here, the packet processor 32), and the packet processor 31 Since no packet processing permission is given to, the load on the packet processor 31 does not increase.

The above assumed packet processor 32
Are shared bus 5, bus interface 2, I / O bus 4
, The control packet is read from the data relay buffer 2002 and stored in the reception buffer 302. Then
The packet processing unit 304 reads the control packet from the reception buffer 302, analyzes the contents of the packet, performs necessary processing, and writes the control packet to be transmitted to the transmission buffer 303. The transmission / reception control unit 3011 reads the control packet written in the transmission buffer 303 from the transmission buffer 303 and transmits the control packet to the data relay unit 1 via the shared bus 5, the bus interface 2, and the I / O bus 4. Then, the control packet reaches the opposite device via the corresponding communication channel 1002.

As described above, a new control packet received from the communication channel is prevented from being read by a packet processor having a higher load than a certain level, whereby the control packet is distributed to a packet processor having a lower load level. The load of each packet processor averages over time. As a result, a specific packet processor receives control packets in a concentrated manner, and the load on the packet processor is significantly increased, and processing delay due to a large number of control packets remaining in the reception buffer 302 can be suppressed. (Embodiment 2) In Embodiment 1, when the load levels of all the packet processors are larger than a predetermined threshold, all the packet processors refuse to receive a new control packet, and Distribution control unit 21
Cannot distribute new control packets. Also, a packet processor whose load level is smaller than a predetermined value can receive a new control packet, but among the receivable packet processors, a packet processor having a lower load level is selected. Can not do. Therefore, if the response of the transmission / reception control unit is delayed according to the load level as described below, this point is improved.

The overall configuration of the load-balanced packet parallel processing device according to the second embodiment is the same as that of the load-balanced packet parallel processing device of the first embodiment (FIG. 1). The configuration of the processor cards 31 to 35 is the same as that of the first embodiment, and the following description will be made with reference to FIG.
However, since the operation procedure of the transmission / reception control unit is different from that of the first embodiment, reference numeral 301 of the transmission / reception control unit is used here.
2 is used.

That is, in the second embodiment, the time for responding to the packet processing request signal of the packet distribution control unit 21 is changed according to the load level determined by the load level determining unit 305.

The following is a more detailed description. First, it is assumed that the states of the packet processors 31 to 35 are the same as in the first embodiment.

In this case, the packet distribution control unit 21 detects a control packet from the communication channel 1002 and inputs a packet processing request signal to the packet processors 31 to 35 via the shared bus 5. The transmission / reception control unit 3012 of each packet processor receiving the packet processing request signal requests the load level of its own packet processor from the load level determination unit 305, and the load level determination unit 305 receiving this request determines the load level ( Embodiment 7 below
-10), and transmits and receives the load level.
Notify. The above procedure is exactly the same as in the above embodiment.

As described above, the packet transmission / reception control unit 3012 receiving the load level from the load level determination unit 305
Determines a delay time for outputting a packet processing response signal to the packet distribution control unit 21 according to the load level,
The packet distribution control unit 2 delays the time by the delay time.
1 to output a packet processing response signal. The delay time according to the load level is assumed, for example, as shown in Table 2 below.

[0039]

[Table 2]

Here, each of the packet processors 31 to 35
Is the same as the state shown in Table 1, the packet processing response signal notification time from the transmission / reception control unit 3012 of the packet processors 31 to 35 to the packet distribution control unit 21 is as shown in Table 3 below.

[0041]

[Table 3]

As described above, the transmission / reception control unit 3012
The delay time is determined in accordance with the load level, and the packet processing response signal is output to the packet distribution control unit 21 with a delay corresponding to the delay time. The packet processing response signal reaches the packet distribution control unit 21 earliest.

At this time, which of the response signals of the packet processor 32 and the packet processor 35 arrives at the packet distribution control unit 21 earlier depends on the characteristics of the hardware and the like, but the delay time is one unit or two units. Packet processing response signals of the packet processors 31, 33, and 34 of the
Packet processor 32, packet processor 3 in units
5 will not arrive earlier than the packet processing response signal. Subsequent processing is the same as in the first embodiment, and a description thereof will not be repeated.

As described above, the transmission / reception control unit 3012
By giving a delay time in response to the packet processing request signal of the packet distribution control unit 21 in accordance with the load level of the packet processor, the packet distribution control unit 21 allows the packet processor of the group with the smallest load level to perform packet processing. It is possible to give.

Unlike the first embodiment, in the second embodiment, there is no case where all the packet processors refuse to receive, and even if the load level of all the packet processors is high, the packet distribution control unit 21 Receives a packet processing response signal from any of the packet processors,
Control packets can be distributed. In addition, the packet processor with a small load level outputs a packet processing response signal to the packet distribution control unit 21 earlier.
The distribution of control packets can be controlled more finely,
The load can be more evenly distributed. (Embodiment 3) The overall configuration of a load balancing packet parallel processing device according to the third embodiment is the same as the configuration of the load balancing packet parallel processing device of the first embodiment (FIG. 1).
Also, the configuration of the packet processor is the same as that shown in FIG. 2, and the operation procedure of the transmission / reception control unit is the same as that described in the first embodiment. Is used. In addition, since the feature is that the load level is determined according to the amount of packets stored in the reception buffer, the following description will be made using the reference numeral 3051 as the load level determination unit.

First, the states of the packet processors 31 to 35 are assumed as shown in Table 4 below. Communication channel 1002
Is assumed to have arrived at the relay card 1 from the communication channel 1002.
From when the control packet arrives at the relay card 1 to when the transmission / reception control unit 3011 requests the load level from the load level determination unit 3051 is the same as in the first embodiment.

[0047]

[Table 4]

The load level determination unit 3051 receives a request for a load level from the transmission / reception control unit 3011 and detects the number of control packets held in the reception buffer 302. Each packet processor is in the state shown in Table 4, and in this state, the number of control packets held in the reception buffer 302 is the number described in the load column of Table 4.

Here, the relationship between the control packet held in the reception buffer 302 and the load level in the third embodiment is defined as follows.

Number of control packets: 0 => Low load level Number of control packets: 1 to 5 => Medium load level Number of control packets: 6 or more => High load level Accordingly, the load levels of the packet processors 31 to 35 are as follows. become.

Packet processor 31: High load level Packet processor 32: Low load level Packet processor 33: Medium load level Packet processor 34: Medium load level Packet processor 35: Low load level As described above, the load level determination unit 3051 The load level is determined according to the amount of control packets held in the reception buffer 302, and the load level is notified to the transmission / reception control unit 3011. The processing after the transmission / reception control unit 3011 receives the load level is the same as that in the first embodiment, and thus the description is omitted.

As described above, the load level determining unit 3051
Determines the load level according to the amount of control packets held in the reception buffer 302 of the packet processor, and the transmission / reception control unit 3011
According to the load level determined by 51, it is determined whether or not to respond to the packet processing request signal of the packet distribution control unit 21.

Therefore, the packet distribution control unit 21 can give packet processing permission only to a packet processor in which the amount of control packets held in the reception buffer 302 is smaller than a predetermined value. The amount of control packets held in the reception buffer 302 of the processor can be averaged. As a result, it is possible to suppress a processing delay caused by a large number of control packets remaining in the reception buffer 302 of a specific packet processor. (Embodiment 4) The overall configuration of a load balancing packet parallel processing device according to the fourth embodiment is the same as the configuration of the load balancing packet parallel processing device according to the first embodiment (FIG. 1). Also, the configuration of the packet processor is the same as the configuration shown in FIG. 2, and the operation procedure of the transmission / reception control unit is the same as that described in the first embodiment, and thus reference numeral 3011 is used. Furthermore, since the feature here is that the load level is determined according to the amount of control packets held in the transmission buffer 303, the following description will be made using 3052 as a reference numeral of the load level determination unit.

First, the states of the packet processors 31 to 35 are set to the states shown in Table 5.

The assumption that the control packet arrives at the relay card 1 from the communication channel 1002 is the same as that of the first embodiment. After the control packet arrives at the relay card 1 from the communication channel 1002, the transmission / reception control unit 301 Is the same as that of the first embodiment until the request is made to the load level determining unit 3052 for the load level.

[0056]

[Table 5]

The load level determining unit 3052 receives a request for a load level from the transmission / reception control unit 301, and detects the number of control packets held in the transmission buffer 303. Here, the relationship between the control packet held in the transmission buffer 303 and the load level is defined as follows.

Number of control packets: 0 => Low load level Number of control packets: 1 to 5 => Medium load level Number of control packets: 6 or more => High load level Accordingly, the load levels of the packet processors 31 to 35 are as follows. become.

Packet processor 31: High load level Packet processor 32: Low load level Packet processor 33: Medium load level Packet processor 34: Medium load level Packet processor 35: Low load level As described above, the load level determination unit 3052 The load level is determined according to the amount of control packets held in the transmission buffer 303, and the transmission / reception control unit 3011 receives the load level of the packet processor. Subsequent processing is the same as in the third embodiment.

As described above, the load level determining unit 3052
Determines the load level in accordance with the amount of control packets held in the transmission buffer 303 of the packet processor, and the transmission / reception control unit 3011
By determining whether to respond to the packet processing request signal of the packet distribution control unit 21 according to the load level determined by the packet distribution control unit 52, the packet distribution control unit 21 determines the amount of control packets held in the transmission buffer 303. It is possible to distribute control packets only to packet processors having a value smaller than a predetermined value, and it is possible to average the amount of control packets held in the transmission buffer 303 of each packet processor. As a result, it is possible to suppress a processing delay caused by a large number of control packets remaining in the transmission buffer 303 of a specific packet processor. (Embodiment 5) The overall configuration of a load balancing packet parallel processing device according to the fifth embodiment is the same as the configuration of the load balancing packet parallel processing device according to the first embodiment (FIG. 1). Also, the configuration of the packet processor is the same as that shown in FIG. 2, and the operation procedure of the transmission / reception control unit is the same as that described in the first embodiment. Is used.

Further, the present embodiment is characterized in that the load level of its own packet processor is determined according to the amount of control packets during which the processing by the packet processing unit 304 is suspended.
The following description is made using 3053 as a reference numeral of the load level determination unit.

First, the states of the packet processors 31 to 35 are assumed as shown in Table 6. The rightmost column of Table 6 indicates the number of processes that the packet processing unit 304 is interrupting. The assumption that the control packet arrives at the relay card 1 from the communication channel 1002 is the same as in the first embodiment, and after the control packet arrives at the relay card 1 from the communication channel 1002, the transmission / reception control unit 3011 sets the load level. Deciding part 3053
The operation up to requesting the load level is the same as in the first embodiment.

[0063]

[Table 6]

The load level determining unit 3053 receives the request of the load level from the transmission / reception control unit 3011 and detects the number of processes suspended by the packet processing unit 304. here,
The relationship between the number of control packets and the load level during the interruption of the processing by the packet processing unit 304 in the fifth embodiment is defined as follows.

Number of control packets: 0 => Low load level Number of control packets: 1 to 5 => Medium load level Number of control packets: 6 or more => High load level Accordingly, the load levels of the packet processors 31 to 35 are as follows. become.

Packet processor 31: High load level Packet processor 32: Low load level Packet processor 33: Medium load level Packet processor 34: Medium load level Packet processor 35: Low load level As described above, the load level determination unit 3053 The load level is determined according to the amount of processing during which the packet processing unit 304 is suspended, and the transmission / reception control unit 3011 receives the load level of the packet processor. Subsequent processing is the same as in the third embodiment.

As described above, the load level determining unit 3053
Determines the load level in accordance with the amount of control packets during which the processing of the packet processing unit 304 of the packet processor is suspended, and the transmission / reception control unit 3011
3 determines whether or not to respond to the packet processing request signal of the packet distribution control unit 21 in accordance with the load level determined by the packet distribution control unit 3, so that the packet distribution control unit 21 Control packets can be distributed only to packet processors whose amount is smaller than a predetermined value, and the amount of control packets during which the processing of the packet processing unit 304 of each packet processor is suspended can be averaged. As a result, it is possible to suppress a processing delay caused by the packet processing unit 304 of the specific packet processor holding a large number of interrupted control packets. (Embodiment 6) The overall configuration of a load balancing packet parallel processing device according to the sixth embodiment is the same as the configuration of the load balancing packet parallel processing device according to the first embodiment (FIG. 1). Also, the configuration of the packet processor is the same as that shown in FIG. 2, and the operation procedure of the transmission / reception control unit is the same as that described in the first embodiment. Is used.

Further, the feature here is that the load level is determined in accordance with the type of processing executed by the packet processing unit 304. Therefore, the following description will be made using 3054 as a reference numeral of the load level determination unit. do.

Hereinafter, the operation will be described. First, the states of the packet processors 31 to 35 are assumed as shown in Table 7. The assumption that the control packet arrives at the relay card 1 from the communication channel 1002 is the same as in the first embodiment, and after the control packet arrives at the relay card 1 from the communication channel 1002, the transmission / reception control unit 3011 sets the load level. The operation up to requesting the load level from the determination unit 3054 is also the same as in the first embodiment.

[0070]

[Table 7]

The load level determination unit 3054 receives a request for a load level from the transmission / reception control unit 3011 and analyzes the type of processing performed by the packet processing unit 304. Here, the relationship between the processing performed by the packet processing unit 304 and the load level in the sixth embodiment is defined as follows.

Processing: normal control packet processing, idle state => low load level Processing: executing consistency check of shared memory 6 => during load level Processing: processing consistency recovery of management table on shared memory 6 Medium => high load level Accordingly, the load levels of the packet processors 31 to 35 are as follows.

Packet processor 31: Low load level Packet processor 32: Low load level Packet processor 33: High load level Packet processor 34: Medium load level Packet processor 35: Low load level As described above, the load level determining unit 3054 The load level is determined in accordance with the type of processing performed by the packet processing unit 304, and the transmission / reception control unit 3011 receives the load level of the packet processor. Subsequent processing is the same as in the third embodiment.

As described above, the load level determining unit 3054
Determines the load level according to the type of processing performed by the packet processing unit 304 of the packet processor, and the transmission / reception control unit 301 determines the load level according to the load level determined by the load level determination unit 3051. The packet distribution control unit 21 determines whether or not to respond to the packet processing request signal of the packet processing unit 30.
The control packets can be distributed in accordance with the type of the processing performed by the control unit 4 and a new control packet can be prevented from being distributed to the packet processor performing the processing with high urgency. As a result, the packet processing unit 304 of the packet processor can concentrate on the management data inconsistency recovery processing on the shared memory 6 and perform the processing.
The system can be quickly restored to the normal state. In addition, it is possible to suppress the processing delay caused by the reception buffer 302 of the packet processor holding many control packets during the mismatch recovery processing. (Embodiment 7) The overall configuration of a load balancing packet parallel processing device according to the seventh embodiment is the same as that of the load balancing packet parallel processing device according to the first embodiment (FIG. 1). Also, the configuration of the packet processor is the same as the configuration shown in FIG. 2, and the transmission / reception control unit is the same as the content described in the second embodiment for determining the delay time according to the load level. 3012 is used as a reference numeral of the transmission / reception control unit.

Further, as in the third embodiment, the feature is that the load level is determined according to the amount of control packets held in the reception buffer 302. The following description will be made using 3051 as an example.

That is, the procedure up to the determination of the load level by the load level determination section 3051 is the same as that of the third embodiment, and the procedure by which the packet transmission / reception section 3012 determines the delay time according to the load level determined in this way. Is as described in the second embodiment. The operation after the load level is determined by the load level determining unit 3051 is the same as that of the second embodiment.

As a result, the packet processor that receives the new control packet can quickly send the packet processing response signal to the packet distribution control unit 2 of the packet processor 32 or the packet processor 35 whose delay time is 0 unit.
The packet processor reaches the packet processor 1 and distributes the packet to a packet processor having a small amount of control packets held by the reception buffer 302.

As described above, the load level determining unit 3051
Determines the load level in accordance with the amount of control packets held in the reception buffer 302 of the packet processor.
In response to the load level determined by 51, the time for responding to the packet processing request signal of the packet distribution control unit 21 is changed, and the packet distribution control unit 21 determines whether the amount of control packets held in the reception buffer 302 is small. The packet processing permission is given to the processor.

As a result, the packet distribution control unit 21 can determine a packet processor that distributes control packets more finely in accordance with the amount of control packets held in the reception buffer than in the third embodiment. Thus, the amount of control packets held in the reception buffer 302 of each packet processor can be further averaged. Then, it is possible to suppress a processing delay due to a large number of control packets remaining in the reception buffer 302. (Embodiment 8) The overall configuration of a load balancing packet parallel processing device according to the eighth embodiment is the same as the configuration of the load balancing packet parallel processing device according to the second embodiment (FIG. 1). Although the basic configuration of each packet processor is the same as the configuration shown in FIG. 2, here, since the same method as in the second embodiment is adopted, reference numeral 3012 is used as the reference numeral of the packet transmission / reception unit. Since the load level is determined in the same manner as in the fourth embodiment, reference numeral 3052 is used as a reference for the load level determination unit.

First, the states of the packet processors 31 to 35 are the same as those in the fourth embodiment, and the communication channel 1
Assume that the control packet has arrived at the relay card 1 from 002. After the control packet arrives at the relay card 1 from the communication channel 1002, the transmission / reception control unit 3012 requests the load level from the load level determination unit 3052, and the load level determination unit 3052 transmits the control packet stored in the transmission buffer 303. The load level is determined according to the amount of the load level, the operation until the transmission / reception control unit 3012 receives the load level from the load level determination unit 3052, and the load level determination unit 30
The value of the load level determined by 52 is the same as in the fourth embodiment. Further, the operation from the reception of the transmission / reception control unit 3012 from the load level from the load level determination unit 3052 to the output of the packet processing response signal until the packet processing permission is given to any of the packet processors is the same as that of the second embodiment. Is the same.

As described above, the load level determining unit 3052
Determines the load level in accordance with the amount of control packets held in the transmission buffer 303 of the packet processor.
The time for responding to the packet processing request signal of the packet distribution control unit 21 is changed according to the load level determined by the packet distribution control unit 52, and the packet distribution control unit 21 The packet processing permission is given to the processor. As a result, the packet distribution control unit 21 can determine a packet processor that distributes control packets more finely in accordance with the amount of control packets held in the transmission buffer 303 than in Embodiment 4. The amount of control packets held in the transmission buffer 303 of the packet processor can be further averaged. Then, it is possible to suppress a processing delay caused by a large number of control packets remaining in the transmission buffer 303. (Embodiment 9) The overall configuration of a load balancing packet parallel processing device according to the ninth embodiment is the same as the configuration of the load balancing packet parallel processing device according to the first embodiment (FIG. 1). Since the operation procedure of the transmission / reception control unit is the same as that in the second embodiment, reference numeral 3012 is used as the reference numeral of the transmission / reception control unit. Further, the method for determining the load level is the same as in the fifth embodiment.
Therefore, 3053 is used as a reference for the load level determination unit.

First, the states of the packet processors 31 to 35 are the same as those in the fifth embodiment, and the communication channel 1
Assume that the control packet has arrived at the relay card 1 from 002. After the control packet arrives at the relay card 1 from the communication channel 1002, the transmission / reception control unit 3012 requests the load level from the load level determination unit 3053, and the load level determination unit 3053 transmits the control packet stored in the transmission buffer 303. The load level is determined according to the amount of the load level, the operation until the transmission / reception control unit 3012 receives the load level from the load level determination unit 3053, and the load level determination unit 30
The value of the load level determined by 53 is the same as in the fifth embodiment. Also, the operation from the transmission / reception control unit 3012 receiving the load level from the load level determination unit 3053 to outputting the packet processing response signal until packet processing permission is given to any packet processor is the same as that of the seventh embodiment. Is the same.

As described above, the load level determining unit 3053
Determines the load level according to the amount of control packets during which the processing of the packet processor 304 of the packet processor is suspended.
3 responds to the packet processing request signal of the packet distribution control unit 21 in accordance with the determined load level, and the packet distribution control unit 21
The packet processing permission is given to the packet processor with a small amount of control packets during the interruption of the processing. As a result, the packet distribution control unit 21 can determine a packet processor that distributes control packets more finely according to the amount of control packets during which the processing of the packet processing unit 304 is interrupted than in the fifth embodiment. The amount of control packets during which the processing of the packet processing unit 304 of each packet processor is interrupted can be further averaged. Then, it is possible to suppress the processing delay caused by the packet processing unit 304 holding a large number of control packets that are being interrupted. (Embodiment 10) The overall configuration of a load-balanced packet parallel processing apparatus according to the tenth embodiment is the same as the configuration of the load-balanced packet parallel processing apparatus according to the second embodiment (FIG. 1). Also, the operation procedure of the transmission / reception control unit is described in
Therefore, reference numeral 3012 is used.
Further, the operation procedure of the load level determination unit is the same as that of the fifth embodiment
Therefore, the reference numeral 3054 is used.

First, the states of the packet processors 31 to 35 are the same as in the case of the sixth embodiment.
Assume that the control packet has arrived at the relay card 1 from 002. After the control packet arrives at the relay card 1 from the communication channel 1002, the transmission / reception control unit 301 requests a load level from the load level determination unit 3054, and the load level determination unit 3054 determines the type of the processing performed by the packet processing unit 304. The load level is determined according to the
The operation until 01 receives the load level from the load level determining unit 3054 and the value of the load level determined by the load level determining unit 3054 are the same as those in the sixth embodiment. Also,
The packet transmission / reception control unit 3012
The operation from receiving the load level from 54 to outputting a packet processing response signal until packet processing permission is given to one of the packet processors is described in the seventh embodiment.
Is the same as

As described above, the load level determining unit 3054
Determines the load level according to the type of processing performed by the packet processing unit 304 of the packet processor, and the transmission / reception control unit 3012 determines the load level according to the load level determined by the load level determination unit 3054. The packet distribution control unit 21 changes the time for responding to the packet processing request signal of 21, and gives the packet processor permission to the packet processor according to the type of processing performed by the packet processing unit 304. As a result, the packet distribution control unit 21 can determine the packet processor that distributes the control packet more finely than in the sixth embodiment, and does not distribute the new control packet to the packet processor that performs the processing with high urgency. You can do so. And
The packet processing unit 304 of the packet processor can concentrate on the process of restoring the inconsistency of the management data on the shared memory 6, and can quickly recover the system to the normal state. In addition, it is possible to suppress the processing delay caused by the reception buffer 302 of the packet processor holding many control packets during the mismatch recovery processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a load balancing packet parallel processing device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a packet processor of the load balancing packet parallel processing device of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional packet parallel processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data relay means 2 Bus interface 4 I / O bus 5 Shared bus 6 Shared memory card 21 Packet distribution control unit 31-35 Packet processor 302 Receive buffer 303 Transmission buffer 304 Packet processing unit 305 Load level determination unit 1001-100N Communication channel 2001 To 200N Data relay buffer 3011 to 3012 Transmission / reception control unit 3051 to 3054 Load level determination unit

Claims (7)

[Claims] At least one communication channel, a plurality of packet processors for processing control packets received from the communication channel, and a packet distribution control for distributing control packets received from the communication channel to the plurality of packet processors. When a new control packet arrives at the communication channel, the packet distribution control unit outputs a packet processing request to the plurality of packet processors, and permits the packet processor which responded to the packet processing request earliest to process the packet processing request. In the load-distributed packet parallel processing apparatus, the processor card includes: a load level determining unit that determines a load level of the own packet processor; and a load level determined by the load level determining unit.
A load distribution type packet parallel processing device, comprising: a transmission / reception control unit for performing a response process to the packet processing request. 2. The transmission / reception control section according to a load level of a predetermined threshold value determined by the load level determination section,
2. The load balancing packet parallel processing apparatus according to claim 1, which responds to the packet processing request. 3. The load-distributed packet parallel processing device according to claim 1, wherein the transmission / reception control unit changes a time for responding to the packet processing request according to the load level determined by the load level determination unit. 4. The load level determination unit according to claim 2, wherein the load level determination unit determines the load level according to an amount of control packets held in a reception buffer provided in the packet processor.
Or the load balancing packet parallel processing device according to 3. 5. The load level determination unit according to claim 2, wherein the load level determination unit determines the load level according to an amount of control packets held in a transmission buffer provided in the packet processor.
Or the load balancing packet parallel processing device according to 3. 6. The load distribution according to claim 2, wherein the load level determination unit determines the load level in accordance with the number of control packets during which processing is suspended in a packet processing unit provided in the packet processor. Type packet parallel processing device. 7. The load-distributed packet parallel processing apparatus according to claim 2, wherein the load level determination unit determines the load level according to a type of processing in a packet processing unit provided in the packet processor. .