JPS58210666A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58210666A JPS58210666A JP9312182A JP9312182A JPS58210666A JP S58210666 A JPS58210666 A JP S58210666A JP 9312182 A JP9312182 A JP 9312182A JP 9312182 A JP9312182 A JP 9312182A JP S58210666 A JPS58210666 A JP S58210666A
- Authority
- JP
- Japan
- Prior art keywords
- schottky barrier
- electrode
- periphery
- substrate
- opening part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 11
- 238000009413 insulation Methods 0.000 abstract description 4
- 229910001295 No alloy Inorganic materials 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 2
- 229910045601 alloy Inorganic materials 0.000 description 7
- 239000000956 alloy Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 101100384355 Mus musculus Ctnnbip1 gene Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はショットキバリア・ダイオードの電極構造に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode structure for a Schottky barrier diode.
半導体表面の一部に金属層會接触させてショットキバリ
アダイオードを形成する場合に、通常、第1図に示すよ
うに例えばn型81基板lの表面のslの酸化物(sl
o、 )等からなる絶縁膜2の一部kF7B開してA4
’i蒸着し、Atと81との間の合金層によるショット
キバリア3紫有するダイオードの一方の電ff14’i
r形成する。ダイオードの他方の電極5はnfM基板1
の一部に予め高濃度計拡散層6r形成し、この上にht
’2オーばツク接触させる。When a Schottky barrier diode is formed by contacting a part of the semiconductor surface with a metal layer, it is common to use sl oxide (sl) on the surface of an n-type 81 substrate l as shown in FIG.
A4 by opening a part of the insulating film 2 consisting of
'i evaporated and one side of the diode with a Schottky barrier 3 violet due to an alloy layer between At and 81 ff14'i
r form. The other electrode 5 of the diode is the nfM substrate 1
A high concentration meter diffusion layer 6r is formed in advance on a part of the ht
'2 Over contact.
このよりなAt′4を使用したショットキバリア・ダイ
オード電極において、At電極直下の基板S1がAtに
溶融して基板表面深くアロイビット7ケ生じ、これがダ
イオードの順方同亀圧V、のばらつきやリーク’ilE
流不艮の原因となっている。このようなアロイビットは
同図に示すようにAt[極が周辺部の絶縁膜と重なるA
tの坤い部分の直下では特に顕著である。アロイビット
の弊害を防止する手段として電極周辺部に例えばp型の
拡散階音リング状に形成するガードリング付ショットキ
・ダイオードも提案さnているがガードリングとなる部
分はダイオードとしては無効部分でl)、このため半導
体装置の果槓度か低下したり、ガードリング9層による
寄生サブpnpl’ランリスタ等の動作のおそn2考慮
しなければならないという問題がめった。In this Schottky barrier diode electrode using At'4, the substrate S1 directly under the At electrode melts into At and seven alloy bits are formed deep on the substrate surface, which causes variations in the diode's forward torsion pressure V. leak'ilE
It is the cause of the flow. As shown in the figure, such alloy bits are At [A where the pole overlaps with the peripheral insulation film]
This is especially noticeable just below the t-shaped part. As a means to prevent the adverse effects of alloy bits, a Schottky diode with a guard ring formed in the shape of a p-type diffused scale ring around the electrode has also been proposed, but the guard ring is an ineffective part as a diode. (1) This frequently causes problems such as a reduction in the efficiency of the semiconductor device and the possibility of the operation of parasitic sub-pnpl' run listers due to the nine guard ring layers.
本発明に上記しπ問題’に篇決したものであり、その目
的とするところはショットキバリア・ダイオードにおけ
るV、のばらつきリーク電流不艮紫低減し、半導体装置
の歩留り紫向上することにある。The present invention addresses the above-mentioned π problem, and its purpose is to reduce the variation in leakage current of V in a Schottky barrier diode and to improve the yield of semiconductor devices.
第2図、第3図に本発明によるショットキバリアダイオ
ードの鐘も単純化はnで実施例か示される。このショッ
トキバリアダイオードに、81基板1表面においてショ
ットキバリアrつくるAt電極4tその周辺部の絶縁膜
2との間に「目あき部」8゛紫つくることによりA4電
極と絶縁膜tS間させ、それらの電なりをなくしたもの
である。In FIGS. 2 and 3, simplified embodiments of the Schottky barrier diode according to the present invention are shown. In this Schottky barrier diode, on the surface of the 81 substrate 1, the At electrode 4t that forms the Schottky barrier r is formed, and the insulating film tS is formed between the A4 electrode and the insulating film tS by creating a ``open part'' 8゛ purple between the At electrode 4t and the insulating film 2 around it. This eliminates the need for electricity.
このように同辺部に「目あI!部J87有するショット
キバリア電極は在米のようIcAt膜周辺部がP縁膜に
重なることによる摩みの増加がなく、シたがってショッ
トキバリア周辺部のAt1iが減少さnアロイビットが
なく、電界集中によるリーク電訛不良やV、のばらつ@
tなく丁ことができる。In this way, the Schottky barrier electrode with the "eye I! part J87" on the same side does not have an increase in wear due to the IcAt film periphery overlapping the P edge film unlike in the United States, and therefore the Schottky barrier periphery At1i is reduced and there are no alloy bits, resulting in leakage voltage defects due to electric field concentration and variations in V.
It can be done without t.
なお、基板にオーミック接触する他のAt11L極51
1J[おいてはn 拡散層61Cより基板と同1位とな
るためビットの影響はきわめて少ない。In addition, the other At11L pole 51 is in ohmic contact with the substrate.
1J[, the n diffusion layer 61C is ranked the same as the substrate, so the influence of the bit is extremely small.
ところでこのように周辺部に「目めき部」【設けた電極
から配−を引き出す場合にこのままでに都合がわるい。By the way, it is inconvenient as it is when pulling out the wiring from the electrode provided in the peripheral area.
第4図は本発明によるショットキバリア・ダイオード電
極4より配線音引き出すためにパッシベイション膜(例
えばポリイミド系樹脂膜)9のスルーホール紫通して2
#目の1を配線10kAt電極4に接続した場合の実施
fIl會示すものである。FIG. 4 shows a through hole 2 in a passivation film (for example, a polyimide resin film) 9 in order to extract wiring sound from a Schottky barrier diode electrode 4 according to the present invention.
This is a diagram showing an implementation when the #1 wire is connected to the 10kAt electrode 4.
第5図は本発明によるショットキバリアダイオード電極
において、配線OQ引き出し側に予めp型拡散#11を
設けることにより、この部分でアロイビットが生じても
pn接合によp電流リーク不良のおこるの?防止した実
施例r示すものである。FIG. 5 shows that in the Schottky barrier diode electrode according to the present invention, by providing a p-type diffusion #11 in advance on the wiring OQ extraction side, even if an alloy bit occurs in this part, will a p-current leak failure occur due to the p-n junction? This figure shows an example of how this was prevented.
なお配線引き出しr行なわない側には絶縁膜2と 1の
間VC「目あき部」8暫設けである。この場合、さらに
全面にポリイミド系樹脂等によるパッシベイション膜で
覆うでもよいことに勿論である。Note that a VC "opening" 8 is temporarily provided between the insulating films 2 and 1 on the side where the wiring is not drawn out. In this case, it goes without saying that the entire surface may be further covered with a passivation film made of polyimide resin or the like.
第6図は本発明勿ショットキバリア・ダイオードl’t
@npnトランジスタに応用した場合の実施例を示すも
のである。同図において、12はp−型サブストレート
81基板、13はn 埋込層、140工ピタキシヤルn
Si層、15Uアイソレーションp+層、16にペース
9層、17はショットキバリア、18はエミッタn 層
、19はコレクタ取り出しn+層である。Figure 6 shows the Schottky barrier diode according to the present invention.
This is an example in which the present invention is applied to an @npn transistor. In the same figure, 12 is a p-type substrate 81 substrate, 13 is an n-buried layer, and 140-layer pitaxial n
A Si layer, a 15U isolation p+ layer, 16 a nine space layer, 17 a Schottky barrier, 18 an emitter n layer, and 19 a collector extraction n+ layer.
以上実施例にて述べたように本発明によればショットキ
バリア電極の周辺部に目あき部會つくることによりその
部分でのアロイビットの発生を少なくシ、ショットキバ
リアダイオードのvPのばらつきケなく丁とともにリー
ク電流不良紫低減し、半導体装置の歩留り全同上する効
果が得らnる。As described in the embodiments above, according to the present invention, by creating a perforated part in the peripheral part of the Schottky barrier electrode, the occurrence of alloy bits in that part can be reduced, and the variation in vP of the Schottky barrier diode can be eliminated and the gap can be reduced. At the same time, leakage current defects are reduced, and the overall yield of semiconductor devices is improved.
、本発明は例えばL S T T T L(Low P
O1yar日hottolce7 Tranai8t
Or Tranststor LOgiO)や高速
リニアエOK適用してきわめて有効である。, the present invention can be applied, for example, to L S T T T L (Low P
O1 year hottolce7 Tranai8t
It is extremely effective when applied to Transtor LOgiO) and high-speed linear air.
第1図はこれまでのショットキバリア拳ダイオードの断
面図、
第2図に本発明によるショットキバリア・ダイオードの
断面図、
第3図に第2図に対応する平面図、
第4図〜第6図は本発明によるショットキノ(リア・ダ
イオードの他の実施例を示す断面図でるる。
1・・・n基板、2・・・絶縁膜、3・・・ショットキ
バリア、4・・・At電極、5・・・他のAtw、極、
6・・・n+拡散層、7・・・アロイビット、8・・・
目あき部、9・・・パッシベイション膜、lO・・・第
2 [i!。
第 1 図
第 3 図
第 4 図
第 5 図
第 6 図Fig. 1 is a sectional view of a conventional Schottky barrier diode, Fig. 2 is a sectional view of a Schottky barrier diode according to the present invention, Fig. 3 is a plan view corresponding to Fig. 2, and Figs. 4 to 6. is a sectional view showing another embodiment of the Schottky rear diode according to the present invention. 1...N substrate, 2...Insulating film, 3...Schottky barrier, 4...At electrode, 5...Other Atw, poles,
6...n+ diffusion layer, 7...alloy bit, 8...
Perforated part, 9... Passivation film, lO... 2nd [i! . Figure 1 Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
ットキバリアを有する半導体装置において、上記金属膜
の少なくともショットキバリアtつくる部分にその周辺
部の半導体表面絶縁膜から離間逼れていることを特徴と
する半導体装置。1. Semiconductors and this! Ii - A semiconductor device having a Schottky barrier between it and a metal film it touches, characterized in that at least the portion of the metal film forming the Schottky barrier t is spaced apart from the semiconductor surface insulating film in its peripheral area. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9312182A JPS58210666A (en) | 1982-06-02 | 1982-06-02 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9312182A JPS58210666A (en) | 1982-06-02 | 1982-06-02 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58210666A true JPS58210666A (en) | 1983-12-07 |
Family
ID=14073683
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9312182A Pending JPS58210666A (en) | 1982-06-02 | 1982-06-02 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58210666A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5031006A (en) * | 1985-06-07 | 1991-07-09 | U.S. Philips Corp. | Semiconductor device having a Schottky decoupling diode |
EP1265295A2 (en) * | 2001-06-04 | 2002-12-11 | Matsushita Electric Industrial Co., Ltd. | Silicon carbide Schottky diode and method for manufacturing the same |
-
1982
- 1982-06-02 JP JP9312182A patent/JPS58210666A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5031006A (en) * | 1985-06-07 | 1991-07-09 | U.S. Philips Corp. | Semiconductor device having a Schottky decoupling diode |
EP1265295A2 (en) * | 2001-06-04 | 2002-12-11 | Matsushita Electric Industrial Co., Ltd. | Silicon carbide Schottky diode and method for manufacturing the same |
EP1265295A3 (en) * | 2001-06-04 | 2004-05-12 | Matsushita Electric Industrial Co., Ltd. | Silicon carbide Schottky diode and method for manufacturing the same |
US6900483B2 (en) | 2001-06-04 | 2005-05-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
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