JPS58185092A - Dynamic circuit device - Google Patents

Abstract

PURPOSE:To perform automatic initial setting and to convert the system into a function, by providing a level deciding circuit, an oscillating circuit, a counter circuit and a timing generator circuit when the power supply is applied to the peripheral circuit part of a dynamic circuit. CONSTITUTION:When the power supply is applied to a memory cell array part 11 and a peripheral circuit part 12, a level deciding circuit 3 detects the application of power supply and delivers a prescribed level. This output signal actuates an oscillating circuit 14, a counter circuit 15 and a timing generator circuit 16. Then the output signal is transmitted to the part 12 via an OR circuit 17. The circuit 15 counts the output of the circuit 14 and delivers a prescribed level at a prescribed count value to stop the actuation of the circuit 14 as well as to give the initial setting to the part 12. In such a way, the initial setting is automatically performed when the power supply is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic circuit device having a dynamic circuit such as a dynamic memory.

Dynamic circuits are widely used as circuit systems for large-scale memories or logic LSIs because they have a small power consumption limit, although there are some difficulties in terms of timing and power supply.

Figure @1 shows a schematic diagram of a conventional dynamic memory, which is one of the dynamic type circuits. In the figure, 1 is a part of a memory cell array, and 2 is a dynamic peripheral circuit part. Generally, the dynamic peripheral circuit section 2 of a memory is a timing generator.

Although it is subdivided into more detailed blocks such as address drivers, decoders, and output circuits, these divisions will not be made here for the sake of explanation. Address signals, various control signals, data input signals, etc. are input to such dynamic peripheral circuit section 2.
Conversely, the dynamic peripheral circuit section 2 outputs a data output signal.

By the way, in a dynamic circuit, each node in the circuit is set to a high or low level in advance, and then when the memory device is driven, information or operation that matches the input signal from the outside is acquired internally. It's getting crowded. Therefore, before the valley drive cycle, it is necessary to set each node to a high level or a low level, so-called precharging and discharging time of each node and the setting operation thereof.

However, the power-on FK of a dynamic memory cannot set each node no matter how long it takes, and as a result, a dummy operation for initial setting is required forcibly from the outside. For example, in the currently widely used 16-bit dynamic memory and 64-bit dynamic memory, after the power is turned on,
It mandates that the RAS input signal be clocked throughout the cycle. However, this requires an extra control circuit outside the memory due to the device design, which is one of the reasons why dynamic memory is difficult to use.
This is also one reason.

The present invention has been developed in view of the above-mentioned points, and an object of the present invention is to provide a dynamic circuit device that can automatically perform an initial setting when power is turned on for a dynamic peripheral circuit section of a dynamic circuit.

Embodiments of the present invention will be described below with reference to the drawings. Second
The figure shows an embodiment of the invention.

In this figure, 11 is a memory cell array part, and 12 is a dynamometer type peripheral circuit part, which constitutes a dynamic memory. Both the memory cell array part 11 and the dynamic type peripheral circuit part 12 are powered by a power source. A voltage Vcc is connected and both are grounded. 13 is the power supply voltage Vcc
This is a level determination circuit that receives the input voltage Vcc, and outputs a high level or a low level depending on the change in the power supply voltage Vcc when it is applied. 14 is an oscillation circuit, and a level judgment circuit 13
is driven by the output of A 15Fi power counter circuit counts the output of the oscillation circuit 14, and after counting the number of power outages, outputs a high level or a low level to stop the operation of the oscillation circuit 14. 16 is a timing generator circuit,
It operates upon receiving the output signal of the oscillation circuit 14, and the output is supplied to the dynamic peripheral circuit section 12 via the OR circuit 17.

In the device configured in this way, when the - source voltage Vcc is applied, the level determination circuit 13 detects it and outputs a high level and then a low level. Therefore, the oscillation circuit 14 is driven, and at the same time, the timing generator circuit 16 is operated by its output signal. The output of the timing generator circuit 16 is then sent to the dynamic type peripheral circuit section 12 via the OR circuit 17, thereby performing a set operation for the dynamic type peripheral circuit section 12 when the power is turned on.

When the oscillation circuit 14 operates, the counter circuit 15 as well as the timing generator circuit 16 operate simultaneously. The counter circuit 15 counts the output of the oscillation circuit 14, and after counting the number of power outages, outputs a high level or a low level to stop the 11 operations of the oscillation circuit 14. Then, when the operation of the oscillation circuit 14 stops, the operation of the timing generator circuit 16 also stops, and the supply of its output to the dynamic peripheral circuit section 12 is also stopped. therefore,
After a certain period of time after the power is turned on, the initial setting for the dynamic peripheral circuit section 12 is completed.

Therefore, according to the embodiment, the initial setting of the dynamic peripheral circuit section 12 can be performed without requiring any forced operation from the outside by simply waiting for a period of time after the power is turned on. This not only significantly reduces the difficulty of using dynamic memory, which has traditionally been considered a problem, but also reduces the cost of the entire memory system, reinforcing the advantages of dynamic memory. It is.

FIG. 3 is a diagram specifically showing the apparatus of the present invention, particularly the level determination circuit 13. As shown in this figure, the level determination circuit 13 includes a level shifter 21, a delay circuit 22, and an inversion circuit 23. The level shifter 21 consists of a series circuit of several stages of transistors, and one end is connected to the Fi power supply voltage Vcc.
, the other end is grounded. Furthermore, the output point A of the level shifter 21 is connected to the input of the delay circuit 22 . Delay circuit 2
It is composed of a resistor made of two transistors and a capacitor, and its output is connected to the input point BK of the inverting circuit 23. The inverting circuit 23 is composed of two transistors. The output point C of this inversion 1 path 23 is the oscillation circuit 14.
is connected to the input of

Such a level determination circuit 13 operates as follows.

Now, when the power is turned on and the voltage Vcc reaches a certain level, the output point A of the level shifter 21 becomes high level. The level change is transmitted to the input point B of the inversion circuit 230 after a certain time delay by the delay circuit 22. Then, when the input point B becomes a high level, the output point C of the inverting circuit 23 changes from a high level to a low level, and when this output point C becomes a low level, the next stage oscillation circuit 14 operates. Start.

Note that in FIGS. 2 and 3, the counter circuit 1
5 stops the operation of the oscillation circuit 14, and the oscillation circuit 1
The operation of the timing generator circuit 16 is strange due to the stoppage of the operation of the oscillation circuit 14 and the timing generator circuit 16 due to the output of the counter circuit 15. Only the operation may be stopped.

Furthermore, although FIGS. 2 and 3 have explained the initial setting for the dynamic peripheral circuit section of the dynamic memory, the present invention is applicable not only to the dynamic memory but also to all other dynamic circuits. It is possible f4.

As detailed above, according to the present invention, the initial setting of the dynamic peripheral circuit section of the dynamic circuit is automatically performed when the power is turned on, thereby reducing the troublesomeness of using the dynamic circuit. Not only can this significantly reduce the amount of noise, but also the cost of the entire system including this dynamic circuit can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of a conventional dynamic type memory, Fig. 2 is a block diagram showing an embodiment of the dynamic type circuit device of the present invention, and Fig. 3 is a circuit specifically showing a part of the device of Fig. 2. It is a diagram. 11...Memory cell array part, 12...Dynamic peripheral circuit part,! 3...Level judgment circuit, 14...
- Oscillation circuit, 15... counter circuit, 16... timing generator circuit. Patent applicant: Oki Electric Industry Co., Ltd. Figure 1

Claims (1)

[Claims] A dynamic circuit with a dynamic peripheral circuit section, a level-sensing circuit that outputs a high or low level depending on changes in power supply voltage, and this level-sensing circuit? A voicing circuit that is controlled by the output from the circuit, a counter circuit that counts the output of this oscillation circuit and outputs a high level or a low level after counting the number of power outages, and inputs the output of the oscillation circuit. 11. A dynamic circuit device comprising: a timing generator circuit that drives the dynamic peripheral circuit section until an output from the counter circuit is obtained.