JPS6220711B2 - - Google Patents
Info
- Publication number
- JPS6220711B2 JPS6220711B2 JP54167327A JP16732779A JPS6220711B2 JP S6220711 B2 JPS6220711 B2 JP S6220711B2 JP 54167327 A JP54167327 A JP 54167327A JP 16732779 A JP16732779 A JP 16732779A JP S6220711 B2 JPS6220711 B2 JP S6220711B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- insulating film
- film
- platinum
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 27
- 229910052697 platinum Inorganic materials 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910021339 platinum silicide Inorganic materials 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 30
- 235000012239 silicon dioxide Nutrition 0.000 description 15
- 239000000377 silicon dioxide Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置特にベース電極とエミツ
タ電極との間隔を極端に短くして抵抗を減少させ
たバイポーラトランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, particularly a bipolar transistor in which the distance between a base electrode and an emitter electrode is extremely shortened to reduce resistance.
バイポーラトランジスタのベース抵抗は集積度
を上げるべくパターンを微細化する程大きくなる
傾向にあり、一方ベース抵抗はトランジスタ動作
速度を制限するからかゝる点では小さいのが望ま
しい。本発明はエミツタ領域の可及的近傍におい
てかつベース領域の全面に亘つてベース電極が被
着するようにし、かつ各種パターニングをセルフ
アラインで実行可能なようにし、こうしてベース
抵抗が極めて小さい高集積化可能バイポーラトラ
ンジスタを提供しようとするものである。本発明
の半導体装置の製造方法は半導体基板のフイール
ド領域に絶縁膜を、また活性領域にベース拡散を
行ない、該基板上に不純物ドープの多結晶シリコ
ンを、またその上に絶縁膜を被着し、かつパター
ニングしたフオトレジスト膜を用いてこれらを選
択エツチングしてエミツタ形成領域上に位置する
順テーパ状の多結晶シリコンおよび絶縁膜部分を
残し、次いでベース電極となる多結晶シリコンの
蒸着を行ない、その後前記フオトレジスト膜を除
去して該膜上の多結晶シリコン層をリフトオフ
し、かゝる状態で、全面に絶縁膜を被着しまたイ
オン打込みを行ないかつ熱処理して前記不純物ド
ープの多結晶シリコンを不純物源とするエミツタ
拡散を行ない、次に前記イオン打込みした絶縁物
のエツチングを行なつて前記エミツタ領域上の順
テーパ状の多結晶シリコンの周囲の絶縁膜のみを
残し、またマスクを使用して該エツチングで露出
した前記ベース電極となる多結晶シリコンのパタ
ーニングを行ない、次いで白金を被着し、かつ熱
処理し、次いで白金のエツチングを行なつて白金
シリサイドとなつた前記多結晶シリコン上の白金
を残して前記絶縁膜上の白金膜を除去することを
特徴とするが、次に図面を参照しながらこれを詳
細に説明する。 The base resistance of a bipolar transistor tends to increase as the pattern becomes finer in order to increase the degree of integration.On the other hand, since the base resistance limits the transistor operating speed, it is desirable to have a small base resistance. The present invention allows the base electrode to be deposited as close as possible to the emitter region and over the entire surface of the base region, and enables various patterning to be performed in self-alignment, thereby achieving high integration with extremely low base resistance. The present invention is intended to provide a possible bipolar transistor. The method for manufacturing a semiconductor device of the present invention includes forming an insulating film in the field region of a semiconductor substrate, performing base diffusion in the active region, depositing impurity-doped polycrystalline silicon on the substrate, and depositing an insulating film thereon. , and selectively etching them using a patterned photoresist film to leave a tapered polycrystalline silicon and insulating film portion located on the emitter formation region, and then vapor depositing polycrystalline silicon that will become a base electrode, Thereafter, the photoresist film is removed and the polycrystalline silicon layer on the film is lifted off. In this state, an insulating film is deposited on the entire surface, and ion implantation and heat treatment are performed to form the impurity-doped polycrystalline silicon layer. Emitter diffusion is performed using silicon as an impurity source, and then the ion-implanted insulator is etched to leave only the insulating film around the tapered polycrystalline silicon on the emitter region, and a mask is used. Then, the polycrystalline silicon exposed by the etching, which will become the base electrode, is patterned, and then platinum is deposited and heat treated, and then the platinum is etched to form platinum silicide on the polycrystalline silicon. The method is characterized in that the platinum film on the insulating film is removed while leaving the platinum, and this will be described in detail below with reference to the drawings.
本発明では先ず第１図ａに示すようにｎ型シリ
コン半導体基板１０にアイソプレーナ等の方法に
より酸化膜１２を作り、該酸化膜で囲まれた活性
領域に基板と反対の導電型本例ではｐ型の不純物
を拡散してベース電極１４を作る。このｎ型シリ
コン基板１０はバイポーラトランジスタのコレク
タ領域となる。次にｂに示すようにｎ型不純物の
ヒ素（As）またはリン（Ｐ）をドープされた
3000〜4000Åの厚みの多結晶シリコン層１６を被
着し、その表面にCVD法により1000Å程度の厚
みの二酸化シリコン膜１８を被着し、更にその上
にフオトレジストを塗布しかつパターニングして
エミツタ形成位置に対応する部分に被着したレジ
スト膜２０を作る。このレジスト膜２０をマスク
にして二酸化シリコンおよび多結晶シリコンのエ
ツチングを行ない、第１図ｃに示す状態にする。
この状態で多結晶シリコンの蒸着を行なうと、第
１図ｄに示す如くなる。２２ａ〜２２ｃが該蒸着
により形成された多結晶シリコン膜である。次い
でｐ型不純物のほう素などを全面にイオン打込み
し、多結晶シリコン膜の導電性を高める。この多
結晶シリコン膜２２ａ，２２ｃはベース電極とな
るものであり、蒸着時にすでにｐ型不純物がドー
プされているなら上記イオン打込みは不要であ
る。その後硫酸ボイル又はプラズマアツシヤーに
よりレジスト膜２０を除去すると、その上の多結
晶シリコン膜２２ｂはリフトオフ法の原理で除去
され、第１図ｅに示すように多結晶シリコン膜２
２ａ，２２ｃが残る。この状態でCVD法により
二酸化シリコンを成長させ、二酸化シリコン層２
４を形成する。CVD法による二酸化シリコンの
成長では、蒸着法と異なり、二酸化シリコンは先
細の多結晶シリコン１６の上に庇状に突出してい
る二酸化シリコン膜１８の下部のくぼみにも侵入
し、全体を完全に包む状態となる。この状態で
900〜1000℃の温度で熱処理し、ｎ型不純物を含
む多結晶シリコン１６から該ｎ型不純物をベース
領域１４へ拡散させ、エミツタ領域２６を作る。
このときｐ型不純物ドープの多結晶シリコン層２
２ａ，２２ｃからベース領域１４への不純物拡散
があるが、これは該ベース領域の不純物濃度を高
めるだけであり、支障はない。更に再びほう素の
イオン打込みを行ない、表面の二酸化シリコン膜
２４をエツチングされやすくする。しかし二酸化
シリコン膜１８の蔭になつた二酸化シリコン膜２
４部分（２４ａで示す）は該膜１８で遮蔽される
からイオン打込みは行なわれず、エツチング特性
に変化はない。この状態でフツ酸などのエツチン
グ液で二酸化シリコンのエツチングを行なうと第
１図ｆに示すようにイオン打込みされた二酸化シ
リコン膜部分２４，１８は除去され、くぼみに入
つた二酸化シリコン膜部分２４ａが残る。次いで
マスクを使用してエツチングを行ない、多結晶シ
リコン２２ａ，２２ｂのうち余分の部分を除去す
る。然るのち白金（Pt）をスパツタし、その後熱
処理する。この熱処理で、多結晶シリコン２２
ａ，２２ｃ，１６上に被着した白金はシリコンと
反応して白金シリサイドを作り、一方、二酸化シ
リコン２４ａ上に被着した白金はそのまゝにとど
まる。そこで白金に対するエツチングを行なうと
第１図ｇに示すように白金シリサイド膜２８ａ，
２８ｂ，２８ｃは残るが、二酸化シリコン２４ａ
上の白金は除去される。 In the present invention, first, as shown in FIG. 1a, an oxide film 12 is formed on an n-type silicon semiconductor substrate 10 by a method such as isoplanar, and an active region surrounded by the oxide film is formed with a conductivity type opposite to that of the substrate. A base electrode 14 is formed by diffusing p-type impurities. This n-type silicon substrate 10 becomes a collector region of a bipolar transistor. Next, as shown in b, it is doped with n-type impurity arsenic (As) or phosphorus (P).
A polycrystalline silicon layer 16 with a thickness of 3000 to 4000 Å is deposited, a silicon dioxide film 18 with a thickness of about 1000 Å is deposited on the surface of the polycrystalline silicon layer 16 by a CVD method, and a photoresist is further applied and patterned to form emitters. A resist film 20 is made that adheres to a portion corresponding to the formation position. Using this resist film 20 as a mask, silicon dioxide and polycrystalline silicon are etched to form the state shown in FIG. 1c.
If polycrystalline silicon is deposited in this state, the result will be as shown in FIG. 1d. 22a to 22c are polycrystalline silicon films formed by the vapor deposition. Next, ions of p-type impurities such as boron are implanted into the entire surface to increase the conductivity of the polycrystalline silicon film. These polycrystalline silicon films 22a and 22c serve as base electrodes, and if they are already doped with p-type impurities at the time of vapor deposition, the ion implantation is not necessary. After that, when the resist film 20 is removed by sulfuric acid boiling or plasma assher, the polycrystalline silicon film 22b thereon is removed by the principle of lift-off method, and the polycrystalline silicon film 22b is removed as shown in FIG. 1e.
2a and 22c remain. In this state, silicon dioxide is grown using the CVD method to form a silicon dioxide layer 2.
form 4. When silicon dioxide is grown by the CVD method, unlike the vapor deposition method, silicon dioxide also invades the depressions at the bottom of the silicon dioxide film 18 that protrudes like an eave over the tapered polycrystalline silicon 16, completely enveloping the entire surface. state. in this state
Heat treatment is performed at a temperature of 900 to 1000° C. to diffuse the n-type impurity from the polycrystalline silicon 16 containing the n-type impurity into the base region 14, thereby forming the emitter region 26.
At this time, p-type impurity-doped polycrystalline silicon layer 2
Although there is impurity diffusion from 2a and 22c to the base region 14, this only increases the impurity concentration in the base region and is not a problem. Further, boron ion implantation is performed again to make the silicon dioxide film 24 on the surface more easily etched. However, the silicon dioxide film 2 is hidden behind the silicon dioxide film 18.
Since the four portions (indicated by 24a) are shielded by the film 18, ion implantation is not performed and there is no change in the etching characteristics. In this state, when silicon dioxide is etched with an etching solution such as hydrofluoric acid, the ion-implanted silicon dioxide film portions 24 and 18 are removed, and the silicon dioxide film portion 24a that has entered the recess is removed, as shown in FIG. remain. Etching is then performed using a mask to remove excess portions of polycrystalline silicon 22a and 22b. After that, platinum (Pt) is sputtered on and then heat treated. With this heat treatment, polycrystalline silicon 22
The platinum deposited on a, 22c, 16 reacts with the silicon to form platinum silicide, while the platinum deposited on silicon dioxide 24a remains intact. Therefore, when etching is performed on platinum, a platinum silicide film 28a, as shown in FIG.
28b and 28c remain, but silicon dioxide 24a
The upper platinum is removed.
第２図ａは第１図ｇの状態の素子つまりバイポ
ーラトランジスタを上から見た状態を示す。ベー
ス領域１４の周囲は厚い酸化膜１２が囲んでお
り、このベース領域に２叉状のベース電極２２
ａ，２２ｃが取付けられている。ベース電極２２
ａ，２２ｃは図面下方で１つになつて引出されて
おり（第１図ｆで説明した多結晶シリコン膜２２
ａ，２２ｃの不要部分の除去とは、該２叉状多結
晶シリコン膜の主として外側部分を除去するため
のもの）、そしてその２叉状部分の中に密嵌状態
でエミツタ電極２６ｂが入り込んでいる。第２図
ｂは第１図ｇの要部のみを示したものであるが、
この第２図ａ，ｂを見れば明らかなようにベース
電極２２ａ，２２ｃはベース領域１４のエミツタ
領域２６を除くほヾ全表面にオーム接触してお
り、従つてベース抵抗は極めて小になる。従来の
バイポーラトランジスタのベース電極配線は第３
図に示すようにその多結晶シリコン電極２２部分
がベースコンタクト窓１４ａにおいてベース領域
１４とオーム接触するに過ぎず、該電極２２を引
出線としてアルミニウムのベース配線が酸化膜１
２上において該電極２２と接続することによりベ
ース電極配線が完成する形式であるので、ベース
領域内での抵抗、電極２２部分の抵抗、電極２２
とベース領域１４との接触部の抵抗等、多くの抵
抗が入ることになる。 FIG. 2a shows the device in the state shown in FIG. 1g, that is, a bipolar transistor viewed from above. The base region 14 is surrounded by a thick oxide film 12, and a bifurcated base electrode 22 is formed in this base region.
a, 22c are attached. Base electrode 22
a and 22c are pulled out as one at the bottom of the drawing (the polycrystalline silicon film 22 explained in FIG.
Removal of unnecessary portions a and 22c is mainly to remove the outer portions of the bifurcated polycrystalline silicon film), and the emitter electrode 26b is tightly fitted into the bifurcated portions. There is. Figure 2b shows only the main part of Figure 1g,
As is clear from FIGS. 2a and 2b, the base electrodes 22a and 22c are in ohmic contact with almost the entire surface of the base region 14 except for the emitter region 26, so that the base resistance is extremely small. The base electrode wiring of conventional bipolar transistors is the third
As shown in the figure, the polycrystalline silicon electrode 22 portion is only in ohmic contact with the base region 14 at the base contact window 14a, and the aluminum base wiring is connected to the oxide film 1 using the electrode 22 as a lead wire.
Since the base electrode wiring is completed by connecting the electrode 22 on the base area, the resistance within the base area, the resistance of the electrode 22 portion, and the electrode 22
A large amount of resistance will be introduced, such as resistance at the contact portion between the base region 14 and the base region 14.
また本発明の製造工程はベース電極配線、エミ
ツタ電極配線、酸化膜２４ａの形成、白金膜のパ
ターニングなど多くの工程がセルフアラインで行
なわれ、従つて高集積度微細パターンの形成が可
能である。 Further, in the manufacturing process of the present invention, many steps such as base electrode wiring, emitter electrode wiring, formation of the oxide film 24a, and patterning of the platinum film are performed in a self-aligned manner, thus making it possible to form highly integrated fine patterns.
以上説明したように本発明によればベース抵抗
の小さい、微細パターンの高集積度化可能バイポ
ーラトランジスタが得られ、LSI用素子などに好
適である。 As described above, according to the present invention, a bipolar transistor with a small base resistance and a fine pattern that can be highly integrated can be obtained, and is suitable for LSI devices and the like.
なお実施例ではｎ型基板使用の場合を例に挙げ
たが、勿論ｐ，ｎ導電型はこの逆にしてもよい。 In the embodiment, an example is given in which an n-type substrate is used, but of course the reverse may be used for p and n conductivity types.
第１図ａ〜ｇは本発明の製造方法の１実施例を
示す工程図、第２図ａ，ｂは本発明によるトラン
ジスタベース部の平面図および断面図、第３図は
従来のトランジスタのベース部の概平面図および
断面図である。
図面で１０は半導体基板、１２はフイールド絶
縁膜、１４はベース領域、１６は不純物ドープの
多結晶シリコン層、１８は絶縁膜、２０はフオト
レジスト膜、２２ａ，２２ｃはベース電極となる
多結晶シリコン層、２４は絶縁膜、２６はエミツ
タ領域、２８ａ〜２８ｃは白金シリサイド層であ
る。
1A to 1G are process diagrams showing one embodiment of the manufacturing method of the present invention, FIGS. 2A and 2B are a plan view and a sectional view of a transistor base portion according to the present invention, and FIG. 3 is a conventional transistor base. FIG. In the drawing, 10 is a semiconductor substrate, 12 is a field insulating film, 14 is a base region, 16 is an impurity-doped polycrystalline silicon layer, 18 is an insulating film, 20 is a photoresist film, and 22a and 22c are polycrystalline silicon serving as base electrodes. 24 is an insulating film, 26 is an emitter region, and 28a to 28c are platinum silicide layers.
Claims (1)
た活性領域にベース拡散を行ない、 該基板上に不純物ドープの多結晶シリコンを、
またその上に絶縁膜を被着し、かつパターニング
したフオトレジスト膜を用いてこれらを選択エツ
チングしてエミツタ形成領域上に位置する順テー
パ状の多結晶シリコンおよび絶縁膜部分を残し、 次いでベース電極となる多結晶シリコンの蒸着
を行ない、その後前記フオトレジスト膜を除去し
て該膜上の多結晶シリコン層をリフトオフし、
かゝる状態で、全面に絶縁膜を被着しまたイオン
打込みを行ないかつ熱処理して前記不純物ドープ
の多結晶シリコンを不純物源とするエミツタ拡散
を行ない、 次に前記イオン打込みした絶縁物のエツチング
を行なつて前記エミツタ領域上の順テーパ状の多
結晶シリコンの周囲の絶縁膜のみを残し、またマ
スクを使用して該エツチングで露出した前記ベー
ス電極となる多結晶シリコンのパターニングを行
ない、 次いで白金を被着し、熱処理を行なつて前記多
結晶シリコン上の白金を白金シリサイドとし、次
いで前記白金シリサイドを残して前記絶縁膜上の
白金を除去することを特徴とする半導体装置の製
造方法。[Claims] 1. An insulating film is formed in the field region of a semiconductor substrate, base diffusion is performed in the active region, and impurity-doped polycrystalline silicon is formed on the substrate.
Further, an insulating film is deposited on top of the insulating film and selectively etched using a patterned photoresist film to leave a tapered polycrystalline silicon and insulating film portion located on the emitter formation region, and then a base electrode is formed. After that, the photoresist film is removed and the polycrystalline silicon layer on the film is lifted off,
In such a state, an insulating film is deposited on the entire surface, and ions are implanted and heat treated to perform emitter diffusion using the impurity-doped polycrystalline silicon as an impurity source, and then the ion-implanted insulator is etched. to leave only the insulating film around the tapered polycrystalline silicon on the emitter region, and pattern the polycrystalline silicon exposed by the etching to become the base electrode using a mask. A method for manufacturing a semiconductor device, comprising depositing platinum, performing heat treatment to convert the platinum on the polycrystalline silicon into platinum silicide, and then removing the platinum on the insulating film, leaving the platinum silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16732779A JPS5690561A (en) | 1979-12-22 | 1979-12-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16732779A JPS5690561A (en) | 1979-12-22 | 1979-12-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5690561A JPS5690561A (en) | 1981-07-22 |
| JPS6220711B2 true JPS6220711B2 (en) | 1987-05-08 |
Family
ID=15847684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16732779A Granted JPS5690561A (en) | 1979-12-22 | 1979-12-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5690561A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666822U (en) * | 1993-03-01 | 1994-09-20 | トヨタ車体株式会社 | Pressure control device for die cushion pin |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58169971A (en) * | 1982-03-30 | 1983-10-06 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPS5961179A (en) * | 1982-09-30 | 1984-04-07 | Fujitsu Ltd | Manufacture of bipolar semiconductor device |
| GB2172744B (en) * | 1985-03-23 | 1989-07-19 | Stc Plc | Semiconductor devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53123083A (en) * | 1977-04-01 | 1978-10-27 | Nippon Telegr & Teleph Corp <Ntt> | Production of semiconductor device |
-
1979
- 1979-12-22 JP JP16732779A patent/JPS5690561A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53123083A (en) * | 1977-04-01 | 1978-10-27 | Nippon Telegr & Teleph Corp <Ntt> | Production of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666822U (en) * | 1993-03-01 | 1994-09-20 | トヨタ車体株式会社 | Pressure control device for die cushion pin |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5690561A (en) | 1981-07-22 |
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