JPS58176939A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58176939A JPS58176939A JP6053282A JP6053282A JPS58176939A JP S58176939 A JPS58176939 A JP S58176939A JP 6053282 A JP6053282 A JP 6053282A JP 6053282 A JP6053282 A JP 6053282A JP S58176939 A JPS58176939 A JP S58176939A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- oxide film
- protective film
- film
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000007789 gas Substances 0.000 claims abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000003607 modifier Substances 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 14
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000007864 aqueous solution Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract 3
- 238000000576 coating method Methods 0.000 abstract 3
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 abstract 2
- 239000000203 mixture Substances 0.000 abstract 2
- 238000007598 dipping method Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 241001349592 Benincasa fistulosa Species 0.000 description 1
- 235000015866 Citrullus vulgaris var fistulosus Nutrition 0.000 description 1
- 206010011732 Cyst Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- CTNCAPKYOBYQCX-UHFFFAOYSA-N [P].[As] Chemical compound [P].[As] CTNCAPKYOBYQCX-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、ホトエツチング法等によｐ−ダターン形成
する際の半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device when forming a p-data pattern using a photoetching method or the like.
一般に、バイプーラ集積回、路等の半導体装置を形成す
るＫは、第１図に示すようなＮｆｉ半導体基板（以下単
に基板と称する）１０表面に二酸化シリコン等の酸化膜
２を形成する。？−の酸化膜２にホトエツチング法等で
所定のパターン形成を行なって開孔部３を形成し、さら
に開孔部３を利用して基板１０表面に不純物を拡散して
所定の半導体素子（ペースおよび工ｔｙタ勢）４．５を
形成してなる。この半導体素子４であるペース等を形成
するＫは、基板１ヒよび酸化膜２の両者の表面にホウ素
シリケートガラス膜（ＢａＯ膜）６を形成しく気相成長
法部による）、開孔部３に対応する基板１の一面にホウ
素を熱拡散する。これによ）、Ｐ型層である素子（ベー
ス）４が形成されることになる。さらに、半導体素子５
であるエミ、り等を形成するために、ＢＡＧ膜６を所定
の／々ターンでエツチングし１開孔部１を形成する。そ
して、基板１およびＢＳＧ膜６０両者の表面にリン砒素
シリケートガラス膜（Ｐ・ム＠ｓＧ膜）８を形成し、開
孔部７に対応する基板１０表面にリンおよび砒素を熱拡
散する。これによシ、Ｎ層である素子（エミッタ）５が
形成される。Generally, in order to form semiconductor devices such as bipolar integrated circuits and circuits, an oxide film 2 such as silicon dioxide is formed on the surface of an Nfi semiconductor substrate (hereinafter simply referred to as a substrate) 10 as shown in FIG. ? A predetermined pattern is formed on the oxide film 2 by photoetching or the like to form an opening 3, and impurities are further diffused onto the surface of the substrate 10 using the opening 3 to form a predetermined semiconductor element (paste and It is made up of 4.5 (Engineers). K, which forms the paste etc. of this semiconductor element 4, forms a boron silicate glass film (BaO film) 6 on the surfaces of both the substrate 1 and the oxide film 2 (using a vapor phase growth method), and the opening 3. Boron is thermally diffused onto one surface of the substrate 1 corresponding to the surface of the substrate 1. As a result, an element (base) 4, which is a P-type layer, is formed. Furthermore, the semiconductor element 5
In order to form emitters, ribs, etc., the BAG film 6 is etched in predetermined turns to form one opening 1. Then, a phosphorus arsenic silicate glass film (P.mu.@sG film) 8 is formed on the surfaces of both the substrate 1 and the BSG film 60, and phosphorus and arsenic are thermally diffused onto the surface of the substrate 10 corresponding to the openings 7. As a result, an element (emitter) 5, which is an N layer, is formed.
〔背景技術の問題点〕 ゛
このようＫして形成される半導体装置に対して、さらに
通常アルミニウム等の配Ｊｉ＠９を形成する。従来、こ
の配線膜９を形成する場合、特に酸化膜２ＫＡターン形
成した際の酸化膜２の段差部分１０の形状によっては、
すなわち例えば急峻であると、アルミニウム等のステッ
グカパレーノ（段差部のカバー状態）が悪化する場合が
ある。そのため、配線膜９のノ臂ターン形成時の際に用
いる工、チング液郷がしみ込んで配線膜９０段切れ（第
１図の１１）が発生するなどの欠点があった。[Problems of the Background Art] ``For the semiconductor device formed by K in this way, a metal layer J@9 of usually aluminum or the like is further formed. Conventionally, when forming this wiring film 9, depending on the shape of the step portion 10 of the oxide film 2 when forming the oxide film 2KA turn,
That is, for example, if the slope is steep, the condition of covering the stepped portion of aluminum or the like may deteriorate. For this reason, there were drawbacks such as the process used when forming the notch turn of the wiring film 9, and the tinging liquid seeping into the wiring film 90, causing the wiring film 90 to be cut (11 in FIG. 1).
これを解決するためＫは、第２図に示すように、酸化膜
２にパターン形成をし死際の酸化膜２０段差部分１０ｔ
−ｆｉＱえば緩・和するように酸化膜２を工、チングす
る必要がある。しかしながら、従来のホトエツチング等
の方法では、上記のような段差部分の形状（チー・帯形
状）を例えば緩和するようにフレキシブルに形成し、均
一なテーパ形状を得ることは困難である。To solve this problem, K formed a pattern on the oxide film 2, as shown in FIG.
-fiQ, it is necessary to process or etch the oxide film 2 so as to soften the effect. However, with conventional methods such as photo-etching, it is difficult to form the step portion (chie/band shape) flexibly so as to soften the shape and obtain a uniform tapered shape.
この発明は、上記の事情を鑑みてなされたもので、基板
の表面上の酸化膜勢の／母ターン形成を施す際、その段
差部分のチー／帯形状を７し中シプルに調整しかつ均一
に形成できるようにして、例えばそのチー／４形状の段
差を緩和して配線膜の段切れ等あ発生を防止できる半導
体装置の製造方法を提供することを目的とする。This invention was made in view of the above-mentioned circumstances, and when forming an oxide film/base turn on the surface of a substrate, the shape of the chi/band at the stepped portion is adjusted to 7, medium sipple, and uniform. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent the occurrence of step breakage or the like in the wiring film by reducing the steps of, for example, a chi/four shape.
すなわち、この発明においては、半導体基板の表面上の
酸化膜等の保護膜に対して、一定の比率の７Ｖオンガス
および酸素からなるプラズマガスを照射する。この後、
保護膜の表面上に保護膜とレゾストの密着力を高める表
面改質剤を塗布する。そして、上記保護膜上に所定のレ
ジストパターンを形成し、このレジストパターン
液童浸す。そして、レジストパターンに対応する保護膜
を工、チングするものである。That is, in this invention, a protective film such as an oxide film on the surface of a semiconductor substrate is irradiated with plasma gas consisting of 7V on gas and oxygen at a constant ratio. After this,
A surface modifier that increases the adhesion between the protective film and the resist is applied to the surface of the protective film. Then, a predetermined resist pattern is formed on the protective film, and this resist pattern is immersed. Then, a protective film corresponding to the resist pattern is etched.
以下図面を参照してこの発明の一実施例について説明す
る。第３図はこの発明に係る製造工程を示すもので、例
えばノ々イポーラ集積回路である半導体装置を製造する
場合である。すなわち、まず第３図（Ａ）Ｋ示すように
基板１０表面上に二酸化シリコン等の保護膜（以下酸化
膜と称する）２を形成する。この酸化膜２の表面上に一
定の混合比率の７Ｖオンガス（ＣＦ４）と酸素（０□）
からなるプラズマガス３ノを照射する。An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a manufacturing process according to the present invention, for example when manufacturing a semiconductor device which is a non-polar integrated circuit. That is, first, as shown in FIG. 3(A)K, a protective film (hereinafter referred to as an oxide film) 2 made of silicon dioxide or the like is formed on the surface of the substrate 10. On the surface of this oxide film 2, 7V on gas (CF4) and oxygen (0□) with a certain mixing ratio
irradiate with 3 plasma gases consisting of:
次に′、図俤）に示すように酸化膜２の表面上にヘキサ
メチルノシラザン勢が主成分の表面改質剤（例えば商品
名ＯＡＰ ） Ｊ ：ｌを塗布する。この表面改質剤３
２により、酸化膜２０表面を改質させ、その表面にレジ
スト３３を塗゛布した場合（第３図０）、酸化膜２とＶ
シスト３３との密着力を高める。そして、図９）に示す
ように基板１上に所定のレノストパターン３４を形成す
る。Next, as shown in FIG. This surface modifier 3
2, when the surface of the oxide film 20 is modified and a resist 33 is applied to the surface (FIG. 3 0), the oxide film 2 and V
Increases adhesion to cyst 33. Then, as shown in FIG. 9), a predetermined Rennost pattern 34 is formed on the substrate 1.
この場合、通常グリベーク（ｐｒ＠ｉ＋ａｋ・）、マス
ク合せ、現偉および４ストベーク（ｐｏｓｔ ｂａｋ・
）からなる工程を経てレジストパターン３４を形成する
ことになる。さらに、゛上記のようにレノなわちレジス
トパターン３４に対応し九酸化膜２の表面上をドライウ
ェル水溶液で浸す、このドライウェル水溶液は、通常写
真に使用される印画紙等の表面安定化のために使用する
安定剤で、工、チンダ液が酸化膜３４とレジス）ＪＪの
間へしみ込む場合、酸化膜Ｓ４がエツチングされる量が
再現性良く安定させるために用いる。In this case, the usual Gribake (pr@i+ak・), Mask Alignment, Present Wei and 4-Stroke (post bak・
), the resist pattern 34 is formed. Furthermore, as described above, the surface of the nine oxide film 2 corresponding to the resist pattern 34 is immersed in the dry well aqueous solution. This stabilizer is used to stabilize the amount of oxide film S4 to be etched with good reproducibility when the tinda solution penetrates between the oxide film 34 and the resist (JJ).
そして、図（ト））Ｋ示すように、レノスト／臂ター／
３４に対応する酸化膜２を選択的に工、チングする。こ
の場合、酸化膜２には一定の角度θ（例えば４０１１程
度）を有するチー・ダ３５が形成される。このチー・ぐ
３５の角度θは、上記図に）に示したようなプラズマガ
ス３１を照射する場合、そのプラズマガス３１である７
レオンガスと酸素の混合比率に応じて、はぼ設定される
と考えられる。このように酸化膜２が選択的にエツチン
グされてなる開孔部３６に、ｄｌロン等を熱拡散して基
板１の表面ＫＰｌｆ層（例えばバイポーラトランジスタ
のベースとなる）４を形成する（図ケ））。Then, as shown in Figure (g)
The oxide film 2 corresponding to 34 is selectively etched. In this case, a chi-da 35 having a certain angle θ (for example, about 4011) is formed in the oxide film 2. When irradiating plasma gas 31 as shown in the above figure, the angle θ of this chi
It is thought that the amount is set depending on the mixing ratio of Leon gas and oxygen. A KPlf layer 4 (for example, a base of a bipolar transistor) on the surface of the substrate 1 is formed by thermally diffusing dlron or the like into the opening 36 formed by selectively etching the oxide film 2 (see the figure). )).
このようにして、基板１の表面に所定の半導体素子４を
形成することができる。そして、この場合、酸化膜２を
選択工、チングして形成する・９ターン（開孔部３６）
のテーパ’／１０を、上記のように例えば４０＠程度で
緩らかＫなるように形成することができる。すなわち、
！ラズマガス３１の照射の際、そのグツダマガス３ノで
あるフレオンガスと酸素の混合比率を設定することによ
り、上記のような開孔部３６０段差部のテーパ形状の角
度０をほぼ所定の値にできる。In this way, a predetermined semiconductor element 4 can be formed on the surface of the substrate 1. In this case, the oxide film 2 is selectively etched to form nine turns (openings 36).
The taper '/10 can be formed to have a gentle K of, for example, about 40@ as described above. That is,
! When irradiating with the plasma gas 31, the angle 0 of the tapered shape of the stepped portion of the aperture 360 as described above can be set to approximately a predetermined value by setting the mixing ratio of Freon gas, which is the plasma gas 3, and oxygen.
しかも、基板１の表面上に狭面改質剤を塗布する工程（
＠３図（Ｂ） ’）およびドライウェル水溶液に浸す工
１！（第３図ｔ）） ） Ｋよシ、上記テーパ形状を再
現性良く安定に形成することができる。Moreover, the step of applying the narrow surface modifier on the surface of the substrate 1 (
@Figure 3 (B) ') and soaking in dry well aqueous solution 1! (Fig. 3 t)) K, the above-mentioned taper shape can be stably formed with good reproducibility.
したがって、酸化膜２のチー１４１０（Ｄ形状を角度４
０″程゛度で緩らかに形成できることによシ、前記第２
図に示すように基板１の表面上にアルミニウム配線膜９
を形成しても、その配線膜９に段切れが発生するなどの
不都合を確実に防止できる。Therefore, the chi 1410 (D shape) of the oxide film 2 is
Because it can be formed gently at a degree of about 0'', the second
As shown in the figure, an aluminum wiring film 9 is formed on the surface of the substrate 1.
Even if the wiring film 9 is formed, it is possible to reliably prevent inconveniences such as occurrence of step breaks in the wiring film 9.
以上詳述したようにこの発明によれば、基板の表面上の
酸化膜等の保護膜にノ譬ターン形成を施す際、そのｔ４
ターンの段差部分のテーノ譬形状を７レキシプルに調整
できしかも再現性良く均一に形成できる。したがって、
例えばそのチー・平形状の段差（角度）を緩和して、基
板の表面上に形成するアルミニウム等の配線膜の段切れ
等の発生を確実に防止できる。そのため、安定な一イＩ
−２集積回路等の半導体装置を確実に製造できるもので
ある。As detailed above, according to the present invention, when forming a pattern on a protective film such as an oxide film on the surface of a substrate, the t4
The shape of the step part of the turn can be adjusted to 7 lexiples and can be formed uniformly with good reproducibility. therefore,
For example, by relaxing the step (angle) of the chi-flat shape, it is possible to reliably prevent the occurrence of step breaks in the wiring film, such as aluminum, formed on the surface of the substrate. Therefore, a stable one
-2 Semiconductor devices such as integrated circuits can be manufactured reliably.
＠１図および第２図は従来の半導体装置の構成を示す断
面図、第３図体）〜Ｃ）はこの発明の一実施例に係る半
導体装置の製造工程を示す図である。
１・・・半導体基板（Ｎ型層）、２・・・酸化膜、４・
・・Ｐ型層（ペース）、６・・・ホウ素シリケートガラ
ス膜、８・・・リン砒素シリケートガラス膜、９・・・
配線膜、３１・・・プラズマガス、３２・・・表面改質
剤、３３・・・レノスト。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図Figures 1 and 2 are cross-sectional views showing the structure of a conventional semiconductor device, and Figures 3) to 3C) are views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. 1... Semiconductor substrate (N-type layer), 2... Oxide film, 4...
... P-type layer (pace), 6... Boron silicate glass film, 8... Phosphorous arsenic silicate glass film, 9...
Wiring film, 31... Plasma gas, 32... Surface modifier, 33... Renost. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2
Claims (1)
定のパターンである開孔部を形成し、この開孔部に対応
する上記基板の表面に半導体素子を形成する工１１にお
いて、上記基板の表面上に形成する上記保護膜の表面上
に一定の混合比率の７レオンガスおよび酸素からなるプ
ラズマがスを照射する工程と、この工程後の上記保護膜
の表面上に保護膜とレジストの密着力を高めるようＫす
る表面改質剤を塗布する工程と、上記保護膜の表面上に
レノストを塗布する工程と、このレゾストに所定のノ母
シーンを形成する工程と、このレゾス）パターンに対応
する上記基板の表面をドライウェル水溶液に浸す工程と
、上記レジストパターンに対応する上記保護膜を選択工
、チングして上記基板の表面上に所定のパターンである
開孔部を形成する工程とからなることを特徴とする半導
体装置の製造方法。Step 11 of forming a protective film on the surface of the semiconductor substrate, forming apertures in a predetermined pattern in the protective film, and forming semiconductor elements on the surface of the substrate corresponding to the apertures; A step of irradiating plasma consisting of 7 Leon gas and oxygen at a certain mixing ratio onto the surface of the above-mentioned protective film formed on the surface of the substrate, and a process of irradiating the surface of the above-mentioned protective film with a protective film and resist after this step. A step of applying a K surface modifier to increase adhesion, a step of applying renost on the surface of the above-mentioned protective film, a step of forming a predetermined matrix scene on this res, immersing the corresponding surface of the substrate in a dry well aqueous solution; and selectively etching and etching the protective film corresponding to the resist pattern to form a predetermined pattern of openings on the surface of the substrate. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6053282A JPS58176939A (en) | 1982-04-12 | 1982-04-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6053282A JPS58176939A (en) | 1982-04-12 | 1982-04-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58176939A true JPS58176939A (en) | 1983-10-17 |
Family
ID=13145009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6053282A Pending JPS58176939A (en) | 1982-04-12 | 1982-04-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58176939A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5707408A (en) * | 1993-04-22 | 1998-01-13 | Yugen Kaisha Libo | Method and apparatus for production of fuel gas |
-
1982
- 1982-04-12 JP JP6053282A patent/JPS58176939A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5707408A (en) * | 1993-04-22 | 1998-01-13 | Yugen Kaisha Libo | Method and apparatus for production of fuel gas |
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