JPS58139471A - Mis field effect transistor - Google Patents
Mis field effect transistorInfo
- Publication number
- JPS58139471A JPS58139471A JP2236382A JP2236382A JPS58139471A JP S58139471 A JPS58139471 A JP S58139471A JP 2236382 A JP2236382 A JP 2236382A JP 2236382 A JP2236382 A JP 2236382A JP S58139471 A JPS58139471 A JP S58139471A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- regions
- source
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims 2
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims description 5
- 108091006146 Channels Proteins 0.000 abstract 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 239000002784 hot electron Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）ＩＩ明の技術公費
本発明はＭＩＳ電界効果トランジスタ（以下、単にＭＯ
Ｓ）ランジスタと記す）に関するもので、特に、短いチ
ャネル長を有するＭＯＳ）ランジスタのバンチスルー耐
圧を高める構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) II Ming technology public funding
The present invention relates to a structure for increasing the bunch-through breakdown voltage of a MOS transistor having a short channel length.
＜ｂ＞技術の背景
大規模集積４１特社人容量メモリには、チャネル長’ｆ
Ｊ＜ １μｍ或いはそれ以下のＭＯＳ）ランジスタが用
いられる。このような矩チャネルＭＯＳトランジスタに
於いては□、従来の数μｍのチャネル長のＭＯＳ）ラン
ジスタには無かった種々の不都合が生じる。<b>Technical background Large-scale integration 41 people capacity memory has a channel length 'f'
A MOS (J<1 μm or smaller) transistor is used. In such a rectangular channel MOS transistor, various disadvantages occur that are not present in conventional MOS transistors having a channel length of several μm.
それらの間層のうち大きなものは、微細パターンの実現
に関するものを別にすると、シ腑−トチャネル効果の発
生、ソース／ドレイン耐圧の低下、ホットエレクトロン
効果の発生である。The major problems among these interlayers, apart from those related to the realization of fine patterns, are the occurrence of a blank channel effect, a decrease in source/drain breakdown voltage, and the occurrence of a hot electron effect.
一方、本発明に利用される技術として、ＳＯ■技術が存
在する。該技術の代表例は、二酸化珪素等の絶縁物層上
に非晶質シリコン層或いは多結晶シリコン層を被着し、
それを単結晶化するものであって、このようにして得た
単結晶シリコン層に素子が形成され、集積回路が形成さ
れる。この場合の基板構成が一般的に、Ｓ ｅ ｍ ｉ
ｃ ｏ ｎ ｄ ｕ ｃ −１ｏｒ ｏｎ Ｉｎ
５ｕｌａｔｏｒと表現されることから、ＳＯｌと呼ばれ
るのである。On the other hand, SO2 technology exists as a technology utilized in the present invention. A typical example of this technology is to deposit an amorphous silicon layer or a polycrystalline silicon layer on an insulating layer such as silicon dioxide,
It is made into a single crystal, and elements are formed on the single crystal silicon layer thus obtained to form an integrated circuit. The substrate configuration in this case is generally S e mi
c o n du c -1 or on In
Since it is expressed as 5ulator, it is called SOl.
（ｃ）従来技術と問題点
本尭明者は、先に前記の諸問題を解決するＭＯＳトラン
ジスタを発明し、特許出願を行った。該発明の詳細は特
開昭５５−１３０１７１号公報に記されているので、此
処ではその要点だけを紹介する。(c) Prior Art and Problems Mr. Honya had previously invented a MOS transistor that solved the above-mentioned problems and filed a patent application. The details of this invention are described in Japanese Patent Application Laid-Open No. 55-130171, so only the main points thereof will be introduced here.
該先願発明は第１図に示す構造を有する。該ＭＯ３）ラ
ンジスタに於ては、まず、基板１の不純物濃度は、ソー
ス（Ｓ）或いはドレイン（Ｄ）であるｎ十領域２．３と
の接合耐圧を十分なものとし、且つ空乏層の無用の伸び
を抑制し得る濃度に設定されている。ｐ十領域４の存在
によって、ドレイン空乏層がソース領域に伸びてパンチ
スルーが生じるのが阻止され、更に、ｐ−領域５．５′
の存在により電界が緩和されてホットエレクトロンの発
生が抑えられると共に、チャネル両端に生ずるエツジ効
果が抑制されて、ｖｔｈに及ぼすチャネル長の影響（シ
１−トチャネル効果）を無くしている。実効的チャネル
長を定める領域６の不純物濃度は所定のＶｔｈを得る値
に設定されている。The prior invention has the structure shown in FIG. In the MO3) transistor, first, the impurity concentration of the substrate 1 is set to have a sufficient junction breakdown voltage with the n+ region 2.3, which is the source (S) or drain (D), and to eliminate the need for a depletion layer. The concentration is set to suppress the elongation of. The presence of the p-region 4 prevents the drain depletion layer from extending into the source region and causing punch-through, and furthermore, the p-region 5.5'
Due to the presence of , the electric field is relaxed and the generation of hot electrons is suppressed, and the edge effect occurring at both ends of the channel is suppressed, thereby eliminating the influence of channel length (sheet channel effect) on vth. The impurity concentration in region 6, which determines the effective channel length, is set to a value that provides a predetermined Vth.
前記ｐ−領域領域５．５′及び前記ｐ領域６上に絶＆ｔ
ｌ１７を介してゲート電極８が設けられている。There is no &t on the p-region region 5.5' and the p-region 6.
A gate electrode 8 is provided via l17.
尚、９はフィールド絶縁膜を示している。Note that 9 indicates a field insulating film.
かかる構造のＭＯＳ）ランジスタに於ては、前記の問題
点はほぼ解決されているのであるが、ＭＯＳトランジス
タが更に小型化した場合には、空乏層が前記ｐ十領域４
の下を通って拡がり、パンチスルーが発生してしまう、
即ち、ｆｓ２図の矢印に示す径路によるブレークダウン
が起るのであるが、小型ＭＯ３）ランジスタに於ては、
実現し得るｐ十領域４の深さには限度があるので、前記
構造ではこの問題は解決されない。In the MOS transistor having such a structure, the above-mentioned problems are almost solved, but when the MOS transistor is further miniaturized, the depletion layer becomes smaller than the p-region 4.
It spreads through the bottom and causes punch-through.
In other words, breakdown occurs along the path shown by the arrow in the fs2 diagram, but in a small MO3) transistor,
Since there is a limit to the depth of the p-region 4 that can be realized, the above structure does not solve this problem.
（ｄ）発明の目的
本発明の目的は、かかる径路によるブレークダウンの発
生することのない短チャネルＭＯ３）ランジスタを提供
することである。(d) OBJECTS OF THE INVENTION An object of the present invention is to provide a short channel MO3) transistor that does not suffer from breakdown due to such paths.
（ａ） １１明の構成
この目的を達成する為、本発明のＭＯＳ）ランジスタは
、絶縁基板上に形成された半導体層、前記半導体層に、
互いに離隔して配設された第一導電型を有する第１の領
域と第２の領域、前記第１の領域と第２の領域との間に
配設された第二の導電型を有する第３の領域、前記第１
の領域と第３の領域との藺に配設された第二導電型で低
不純物濃度を有する第４の領域、前記第２の領域と第３
の領域との藺に配設された第二導電型で低不純物濃度を
有する第５の領域、前記第３の領域下に、当該第３の領
域と前記絶縁基板とに接して配置された第二導電型で高
不純物濃度を有する第６の領域、及び前記第３の領域上
に絶縁膜を介して配設されたゲート電極とを備えた構造
を有する。(a) 11th structure In order to achieve this object, the MOS) transistor of the present invention includes a semiconductor layer formed on an insulating substrate, the semiconductor layer having
a first region and a second region having a first conductivity type and spaced apart from each other; and a second region having a second conductivity type and disposed between the first region and the second region. 3 area, said first
a fourth region having a second conductivity type and a low impurity concentration disposed between the region and the third region;
a fifth region having a second conductivity type and a low impurity concentration disposed in parallel with the region; a fifth region disposed below the third region and in contact with the third region and the insulating substrate; The semiconductor device has a structure including a sixth region of biconductivity type and high impurity concentration, and a gate electrode disposed on the third region with an insulating film interposed therebetween.
（ｆ）発明の実施例
本発明のＭＯＳ）ランジスタは前記Ｓｏｌ構造の基板に
構成される。該ＳＯ１構造の基板を得ることは公知技術
である０本発明の実施に適したＳ０１基板の一例は、シ
リコン圏の厚みが０．３〜１８ｍ５不純物濃度ｌＸｌ０
／ｃｄのｐ型のものである。(f) Embodiments of the Invention A MOS transistor of the present invention is constructed on the substrate having the Sol structure. Obtaining a substrate with the SO1 structure is a known technique. An example of an SO1 substrate suitable for implementing the present invention has a silicon layer with a thickness of 0.3 to 18 m5 and an impurity concentration of lXl0.
/cd p-type.
第３図に本発明のれチャネルＭＯ３）ランジスタの構造
が示される。同図（ａ）は平面図であり、（ｂ）はその
写−Ｘ′断面図である。FIG. 3 shows the structure of a leak-channel MO3) transistor according to the present invention. 3(a) is a plan view, and FIG. 2(b) is a sectional view taken along the line X'.
本発明のｎチャネルＭＯ５トランジスタに於ても、前記
先願発明のＭＯＳ）ランジスタと同様、ｐ＋領域１４が
設けられており、ドレイン空乏層がソース領域に伸びて
パンチスルーが生じるのを阻止している。更に、ｐ−領
域１５．１５’がチャネル領域１６の両側に設けられて
、シーートチャネル効果とホットエレクトロン幼果の発
生を防止してむ）る。ｐ十領域１４の形成はイオン注入
によって実施される。In the n-channel MO5 transistor of the present invention, similarly to the MOS transistor of the prior invention, a p+ region 14 is provided to prevent the drain depletion layer from extending to the source region and causing punch-through. There is. Additionally, p-regions 15,15' are provided on both sides of channel region 16 to prevent sheet channel effects and hot electron seedlings. Formation of the p+ region 14 is performed by ion implantation.
チャネル領域１６の不純物濃度は所定のｖ ｔｈを得る
ように設定されており、該領域の不純物濃度−ｉはイオ
ン注入によって行われる。The impurity concentration of the channel region 16 is set to obtain a predetermined v th, and the impurity concentration -i of the region is achieved by ion implantation.
かかる構造を採ることによって本発明のＭＯＳトランジ
スタは、前記先願発明のＭＯＳ）ランジスタと同様、チ
ャネル長が小であるにもかかわらず、シ１−トチャネル
効果の発生、ソース／ドレイン耐圧の低下、ホットエレ
クトロン効果の発生といった問題を解決しているのであ
るが、更に、前記先■発明のＭＯＳ）ランジスタでは未
解決であった、ｐ十領域の下を通る径路によるブレーク
ダウンの問題も解決されている。By adopting such a structure, the MOS transistor of the present invention, like the MOS transistor of the prior invention, has a small channel length, but does not cause the sheet channel effect or decrease the source/drain breakdown voltage. This solves the problem of the generation of hot electron effects, but also solves the problem of breakdown due to the path passing under the p region, which had not been solved in the MOS transistor of the previous invention. ing.
即ち、本発明のＭＯＳ）ランジスタはＳＯ■基板に形成
され、ｐ十領域１４の下は二酸化珪素の如き絶縁体であ
ることから、ｐ十領域１４の下を通る径路は存在せず、
かかる径路のブレークダウンは生じないのである。That is, since the MOS (MOS) transistor of the present invention is formed on an SO2 substrate and an insulator such as silicon dioxide is formed under the p-region 14, there is no path passing under the p-region 14.
Such path breakdown does not occur.
本発明のＭＯＳ）ランジスタを構成する諸領域はいずれ
もイオン注入によって形成される。第３図の１１は絶縁
体、１２．１３はソース或いはドレイン領域であるｎ十
領域、１７はゲート絶縁膜、１８はゲート電極（ｎ十型
多結晶シリコン）、１９はフィールド絶縁膜である。尚
、第３図には図示されていないが、ソース、ドレイン電
極はｎ十領域１２．１３上に配設され、接続される。The various regions constituting the MOS transistor of the present invention are all formed by ion implantation. In FIG. 3, 11 is an insulator, 12 and 13 are n0 regions which are source or drain regions, 17 is a gate insulating film, 18 is a gate electrode (n0 type polycrystalline silicon), and 19 is a field insulating film. Although not shown in FIG. 3, source and drain electrodes are disposed on and connected to the n+ region 12.13.
（ｇ）発明の詳細
な説明した如く、本発明のＭＯＳ）ランジスタに於ては
、トランジスタの小型化にともなって生じるシーートチ
ャネル効果の発生、ソース／ドレイン耐圧の低下、ホッ
トエレクトロン効果の発生といった問題を解決している
だけでなく、ｐ＋領域１４の下を通る径路によるブレー
クダウンも生じることがないので、ＭＯＳ）ランジスタ
をより小型化し、集積回路を高集積化することが可能と
なる。(g) As described in the detailed description of the invention, in the MOS transistor of the present invention, there are problems such as sheet channel effect, decrease in source/drain breakdown voltage, and hot electron effect that occur as transistors become smaller. Not only does this solve the problem, but breakdown due to the path passing under the p+ region 14 does not occur, making it possible to further downsize MOS transistors and increase the degree of integration of integrated circuits.
第１図及び第２図は先行技術とその問題点を示す図、第
３図は本発明を示す図であって、図に於て、１はｐ型シ
リコン基板、２，１２．３．１３はソース或いはドレイ
ン領域、４．１４はｐ十領域、５，５，１５．１５’は
ｐ−領域、６．１６はチャネル領域、７，１７はゲート
絶縁膜、８゜１８はゲート電極、９，１９はフィールド
絶縁膜、１１は絶縁体基板である。
ｖ １ 閃
隼？ 口
第３１￥１
１1 and 2 are diagrams showing the prior art and its problems, and FIG. 3 is a diagram showing the present invention, in which 1 is a p-type silicon substrate, 2, 12.3.13 is a source or drain region, 4.14 is a p-region, 5, 5, 15.15' is a p- region, 6.16 is a channel region, 7, 17 is a gate insulating film, 8°18 is a gate electrode, 9 , 19 are field insulating films, and 11 is an insulating substrate. v 1 Senhaya? mouth 31 yen 1 1
Claims (1)
いに離隔して配設された第一導電型を有する第１の領域
と第２の領域、前記第１の領域と第２の領域との閾に配
設された第二の導電型を有する第３の領域、前記第１の
領域と第３の領域との闘に配設された第二導電型で低不
純物濃度を有する第４の領域、前記１Ｂ２の領域と第３
の領域との闘に配設された第二部電型で低不純物濃度を
有する第５の領域、前記ＩＩ３の領域下に、当該県３の
領域と前記絶縁基板とに接して配置された第二導電型で
高不純物濃度を有する第６の領域、及び前記１１３の領
域上に絶縁膜を介して配設されたゲート電極とを備えて
なることを特徴とするＭＩＳ電界効果トランジスタ。a semiconductor layer formed on an annular substrate; a first region and a second region having a first conductivity type that are spaced apart from each other in the semiconductor layer; and the first region and the second region. a third region having a second conductivity type disposed at a threshold between the first region and the third region; and a fourth region having a second conductivity type and having a low impurity concentration disposed at a boundary between the first region and the third region. area, the area of 1B2 and the third
a fifth region having a low impurity concentration and of a second voltage type, which is disposed to combat the region II3, and a fifth region disposed under the region II3 in contact with the region II3 and the insulating substrate. A MIS field effect transistor comprising: a sixth region of biconductivity type and having a high impurity concentration; and a gate electrode disposed on the region 113 with an insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2236382A JPS58139471A (en) | 1982-02-15 | 1982-02-15 | Mis field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2236382A JPS58139471A (en) | 1982-02-15 | 1982-02-15 | Mis field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58139471A true JPS58139471A (en) | 1983-08-18 |
| JPH0424877B2 JPH0424877B2 (en) | 1992-04-28 |
Family
ID=12080538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2236382A Granted JPS58139471A (en) | 1982-02-15 | 1982-02-15 | Mis field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58139471A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02306665A (en) * | 1989-05-20 | 1990-12-20 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| US5238857A (en) * | 1989-05-20 | 1993-08-24 | Fujitsu Limited | Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure |
| JP2007214495A (en) * | 2006-02-13 | 2007-08-23 | Oki Electric Ind Co Ltd | Semiconductor device and method for fabrication thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51103778A (en) * | 1975-03-10 | 1976-09-13 | Nippon Telegraph & Telephone | Handotaisochito sonoseizohoho |
| JPS55130171A (en) * | 1979-03-29 | 1980-10-08 | Fujitsu Ltd | Mos field effect transistor |
-
1982
- 1982-02-15 JP JP2236382A patent/JPS58139471A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51103778A (en) * | 1975-03-10 | 1976-09-13 | Nippon Telegraph & Telephone | Handotaisochito sonoseizohoho |
| JPS55130171A (en) * | 1979-03-29 | 1980-10-08 | Fujitsu Ltd | Mos field effect transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02306665A (en) * | 1989-05-20 | 1990-12-20 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| US5238857A (en) * | 1989-05-20 | 1993-08-24 | Fujitsu Limited | Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure |
| JP2007214495A (en) * | 2006-02-13 | 2007-08-23 | Oki Electric Ind Co Ltd | Semiconductor device and method for fabrication thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0424877B2 (en) | 1992-04-28 |
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