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JPS5858747A - Metal oxide semiconductor type semiconductor integrated circuit - Google Patents

Metal oxide semiconductor type semiconductor integrated circuit

Info

Publication number
JPS5858747A
JPS5858747A JP15778081A JP15778081A JPS5858747A JP S5858747 A JPS5858747 A JP S5858747A JP 15778081 A JP15778081 A JP 15778081A JP 15778081 A JP15778081 A JP 15778081A JP S5858747 A JPS5858747 A JP S5858747A
Authority
JP
Japan
Prior art keywords
electrode
silicon substrate
transistor
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15778081A
Other languages
Japanese (ja)
Inventor
Masatoshi Sudo
正俊 須藤
Takeshi Kanemasa
金政 健
Masahiro Kurihara
栗原 正大
Yoshiaki Nishikubo
西久保 嘉昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP15778081A priority Critical patent/JPS5858747A/en
Publication of JPS5858747A publication Critical patent/JPS5858747A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the generation of a parasitic MOSFET by forming a semiconductor layer, which is electrically connected to a semiconductor substrate and to which fixed voltage is applied, between an electrode functioning as the gate electrode of the parasitic MOSFET and the silicon substrate section just under the electrode. CONSTITUTION:A fixed potential electrode 16 is formed into a field oxide film positioned onto the silicon substrate section 15, and the one part 16' is connected to the silicon substrate. According to such constitution, the generation of the parasitic MOSFET is prevented because the electrode 13 has no effect on the silicon substrate section 15. The width l1 of the fixed potential electrode 16 is not limited particularly, and may be equal to the width l2 of the silicon substrate section 15.

Description

【発明の詳細な説明】 本発明はMO3型半導体集積回路に関し、寄生MO8)
ランジスタの発生を防ぐことのできるMOSトランジス
タの構造を提供するものである。
[Detailed Description of the Invention] The present invention relates to an MO3 type semiconductor integrated circuit, and a parasitic MO8)
The present invention provides a MOS transistor structure that can prevent the generation of transistors.

Mo8)ランジスタを回路素子として用いて構成される
MO8型半導体集積回路では、作り込まれたMoSトラ
ンジスタ間に寄生MoSトランジスタの発生する場合が
ある。
Mo8) In an MO8 semiconductor integrated circuit configured using transistors as circuit elements, parasitic MoS transistors may occur between built-in MoS transistors.

第り図は、かかる寄生MO8)ランジスタが発根、2,
3は第1のMOSトランジスタのドレインならびにソー
ス領域、4,6は第2のMOSトランジスタのドレイン
ならびにソース領域、6゜7はゲート酸化膜、8゛、9
はゲート電極、10はフィールド酸化膜、そして、11
.12,13および14は電極である。ところで、図示
するように、電極13が第1のMOSトランジスタと第
2のMo8 )ランジスタとの間に位置するフィールド
酸化繰上にまで延びていると、この電極13に電圧が印
加された場合、に、このフィールド;酸化膜の直下のシ
リコン基板部分15をチャンネルとする寄生MOSトラ
ンジスタが発生するところとなる。
The figure below shows that such parasitic MO8) transistors are rooted, 2,
3 is the drain and source region of the first MOS transistor, 4 and 6 are the drain and source regions of the second MOS transistor, 6°7 is the gate oxide film, 8°, 9
10 is a gate electrode, 10 is a field oxide film, and 11 is a gate electrode.
.. 12, 13 and 14 are electrodes. By the way, as shown in the figure, if the electrode 13 extends to the field oxide layer located between the first MOS transistor and the second Mo8 transistor, when a voltage is applied to the electrode 13, , this field is where a parasitic MOS transistor is generated whose channel is the silicon substrate portion 15 directly below the oxide film.

この寄生MOSトランジスタの発生を防ぐため、3−2 従来はシリコン基板部分15にシリコン基板と同一導電
型の不純物を拡散して高不純物濃度層を形成すること、
あるいは、シリコン基板部分16の ・上のフィールド
酸化膜の厚みを十分に厚くし、電極13の電圧の影響が
シリコン基板部分15に及ばないようにすることなどの
対策が講じられていた。
In order to prevent the generation of this parasitic MOS transistor, 3-2 conventionally, impurities of the same conductivity type as the silicon substrate are diffused into the silicon substrate portion 15 to form a high impurity concentration layer;
Alternatively, measures have been taken such as making the field oxide film on the silicon substrate portion 16 sufficiently thick so that the influence of the voltage of the electrode 13 does not reach the silicon substrate portion 15.

本発明は、これらの対策の1つに新たに加えることので
きる構造を提供するものであり、その特徴は、寄生MO
8)う/ジスタのゲート電極として作用する電極とこの
直下のシリコン基板部分との間に、少くとも1点で半導
体基板に電気的に繋り、かつ所定の固定電圧が印加され
る半導体層もしくは半導体層かちなる固定電位電極を配
設したところにある。
The present invention provides a structure that can be newly added to one of these countermeasures, and its characteristics are as follows:
8) A semiconductor layer or a semiconductor layer electrically connected to the semiconductor substrate at at least one point and to which a predetermined fixed voltage is applied between the electrode that acts as the gate electrode of the transistor and the silicon substrate portion immediately below the electrode. This is where a fixed potential electrode made of a semiconductor layer is provided.

第2図は本発明を適用して構成した本発明の一実施例の
MO8型半導体集積回路の要部の断面構造を例示する図
であり、第1図と向一部分には同一番号を付す。図示す
るように、シリコン基板部分15の上に位置するフィー
ルド酸化膜中に固定電位電極16が設けられ、その1部
16′がシリコン基板へ繋がっている点で第1図で示し
た従来のものと相違している。このような構造とするな
らば、もはや電極13の影響がシリコン基板部分16に
及ぶことはなく、この九め寄生MO3)ランジスタの発
生が阻止される。なお、固定電位電極16の幅e1には
特に制限が存在するものではなく、シリコン基板部分1
50幅g2と同等であってもよい。また、図示する幅よ
りさらに狭いものであってもよい。
FIG. 2 is a diagram illustrating a cross-sectional structure of a main part of an MO8 type semiconductor integrated circuit according to an embodiment of the present invention constructed by applying the present invention, and the same reference numerals are given to the parts opposite to those in FIG. 1. As shown in the figure, a fixed potential electrode 16 is provided in a field oxide film located on a silicon substrate portion 15, and a portion 16' thereof is connected to the silicon substrate. There is a difference between With such a structure, the influence of the electrode 13 no longer reaches the silicon substrate portion 16, and the generation of this parasitic MO3) transistor is prevented. Note that there is no particular restriction on the width e1 of the fixed potential electrode 16;
50 width g2. Further, the width may be even narrower than the width shown in the drawings.

以上説明した本発明の効果確認のため、e2を8μm1
固定電位電極15と電極3およびシリコン基板部分15
との間の二酸化シリコン膜の厚みを600’O入および
300八とした本発明の構造と、固定電位電極をなくし
、電極13の直下の二酸化シリコン膜の厚みを6300
八としかつりを8″°とした従来の構造を比抵抗”6′
・cm (7)      tjN型7リコン基板を出
発材料として用いて得、電極に負の電圧を印加し、何ボ
ルトで寄生MOSトランジスタが生じるかを検討した。
In order to confirm the effect of the present invention explained above, e2 was
Fixed potential electrode 15, electrode 3 and silicon substrate portion 15
The structure of the present invention in which the thickness of the silicon dioxide film between the electrodes 13 and 13 is 600° and 300°, and the fixed potential electrode is eliminated and the thickness of the silicon dioxide film directly under the electrode 13 is 6300°
The conventional structure with a resistivity of 8 and 8" has a resistivity of "6'.
・cm (7) tj A N-type 7 silicon substrate was obtained as a starting material, a negative voltage was applied to the electrode, and it was examined at what voltage a parasitic MOS transistor was generated.

本発明のものでは約50Vの負電圧印加で寄生MO8)
ランジスタが発生する。のに対して、従来構造では約s
oVの負電圧印加で寄生MO8トランジスタが発生し両
者間に明瞭な差異のあることが確認された。
In the present invention, parasitic MO8) is generated when a negative voltage of about 50V is applied.
A transistor is generated. In contrast, in the conventional structure, approximately s
It was confirmed that a parasitic MO8 transistor was generated by applying a negative voltage of oV, and that there was a clear difference between the two.

以上説明したところから−明らかなように、本発明のM
O8型半導体集積回路では、寄生MO3,)ランジスタ
の発生が効果的に防止され、誤動作などの不都合が排除
できる。なお、−上記の説明はN型シリコン基板を出発
材料とする場合を例に行ったが、P型シリコン基板を用
いる場合にも本発明が適用可能であることは言うまでも
ない。
From the above explanation, it is clear that the M of the present invention
In the O8 type semiconductor integrated circuit, the generation of parasitic MO3, ) transistors can be effectively prevented, and inconveniences such as malfunctions can be eliminated. Although the above description has been made using an N-type silicon substrate as a starting material, it goes without saying that the present invention is also applicable to a case where a P-type silicon substrate is used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はMO8型半導体集積回路で2個のトランジスタ
が近接した部分の従来構造を示す断面図、第2図は本発
明の一実施例にかかるMO3型半導体集積回路の構−造
を示す断面図である。    −1・・・・・・シリコ
ン基板、214・・・・・・ドレイン領域、3,6・・
・・・・ソース電極、6,7・・・・・・ゲート酸化膜
、8 、9 、、、、、ゲート電極、10・・・・・・
・・・フィールド酸化膜、15・・・・・・分離用のシ
リコン基板部分、16・・・・・・固定−位電極、16
′・・・・・・シリコ/基板部分へ繋がる固定電位電極
部分。
FIG. 1 is a cross-sectional view showing the conventional structure of a MO8 type semiconductor integrated circuit where two transistors are close to each other, and FIG. 2 is a cross-sectional view showing the structure of an MO3 type semiconductor integrated circuit according to an embodiment of the present invention. It is a diagram. -1...Silicon substrate, 214...Drain region, 3,6...
...Source electrode, 6, 7... Gate oxide film, 8, 9, ..., Gate electrode, 10...
... Field oxide film, 15 ... Silicon substrate part for separation, 16 ... Fixed-position electrode, 16
′...Fixed potential electrode part connected to silicon/substrate part.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の所定域に第1のMo8)ランジスタが作り
込まれ、同第1のMOSトランジスタに近接して前記基
板に第2のMOS)ランジスタが作り込まれ、前記間M
O8)ランジスタ間に位置する分離用半導体基板領域部
分上を覆う絶縁膜の上側に所定の電圧が印加される配線
層が形成きれた構造部分を有し、前記配線層と絶縁膜と
の間に、少なくとも1点で前記半導体基板につながりさ
らに所定の固定電圧が印加される導体層もしくは半導体
層を配置したことを特徴とするMO8型半導体集積回路
A first Mo8) transistor is fabricated in a predetermined area of a semiconductor substrate, a second Mo8) transistor is fabricated in the substrate adjacent to the first Mo8) transistor, and a second Mo8) transistor is fabricated in the substrate in the vicinity of the first Mo8) transistor;
O8) There is a structural part in which a wiring layer to which a predetermined voltage is applied is formed on the upper side of the insulating film covering the isolation semiconductor substrate region located between the transistors, and between the wiring layer and the insulating film. An MO8 type semiconductor integrated circuit, further comprising a conductive layer or a semiconductor layer connected to the semiconductor substrate at at least one point and to which a predetermined fixed voltage is applied.
JP15778081A 1981-10-02 1981-10-02 Metal oxide semiconductor type semiconductor integrated circuit Pending JPS5858747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15778081A JPS5858747A (en) 1981-10-02 1981-10-02 Metal oxide semiconductor type semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15778081A JPS5858747A (en) 1981-10-02 1981-10-02 Metal oxide semiconductor type semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5858747A true JPS5858747A (en) 1983-04-07

Family

ID=15657128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15778081A Pending JPS5858747A (en) 1981-10-02 1981-10-02 Metal oxide semiconductor type semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5858747A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045038A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS62239574A (en) * 1986-04-11 1987-10-20 Nec Corp Read-only memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50131778A (en) * 1974-04-05 1975-10-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50131778A (en) * 1974-04-05 1975-10-18

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045038A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS62239574A (en) * 1986-04-11 1987-10-20 Nec Corp Read-only memory

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