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JPS5745958A - Manufacture of stem for semiconductor device - Google Patents

Manufacture of stem for semiconductor device

Info

Publication number
JPS5745958A
JPS5745958A JP55122656A JP12265680A JPS5745958A JP S5745958 A JPS5745958 A JP S5745958A JP 55122656 A JP55122656 A JP 55122656A JP 12265680 A JP12265680 A JP 12265680A JP S5745958 A JPS5745958 A JP S5745958A
Authority
JP
Japan
Prior art keywords
pin
glass
stem
oxidized film
inexpensively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55122656A
Other languages
Japanese (ja)
Inventor
Takashi Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55122656A priority Critical patent/JPS5745958A/en
Publication of JPS5745958A publication Critical patent/JPS5745958A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Connections Arranged To Contact A Plurality Of Conductors (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a stem having high reliability inexpensively by plating electrolytic gloss Ni on a lead pin of Fe-Ni alloy, sealing the hole of a flange with glass and plating a finishing Ni on the pin and the flang. CONSTITUTION:An electrolytic glass Ni is plated in a thickness of 0.5-1.5mum on a lead pin 15 of an Fe-Ni alloy, is treated at 850 deg.C for 5min, and is then exhausted into the air. The Fe is diffused in the Ni layer with this treatment, is suitably exposed on the surface, and an oxidized film is formed. The pin is inserted into the hole 13 of Fe flange attached with a heat sink 12, and is sealed with glass 13 at 1,000 deg.C in N2. In this case the oxidized film on the surface of the pin is rigidly bonded to the glass. The proper thickness of the oxidized film is 0.07-0.08mg/cm. Thereafter, approx. 1mum thick of slectroless Ni is plated to complete it. With this configuration, the adherence and the airtightness of the wire 22 are preferred, with high reliability in a stem inexpensively.
JP55122656A 1980-09-04 1980-09-04 Manufacture of stem for semiconductor device Pending JPS5745958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55122656A JPS5745958A (en) 1980-09-04 1980-09-04 Manufacture of stem for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55122656A JPS5745958A (en) 1980-09-04 1980-09-04 Manufacture of stem for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5745958A true JPS5745958A (en) 1982-03-16

Family

ID=14841368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55122656A Pending JPS5745958A (en) 1980-09-04 1980-09-04 Manufacture of stem for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5745958A (en)

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