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JPS5735340A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5735340A
JPS5735340A JP11060680A JP11060680A JPS5735340A JP S5735340 A JPS5735340 A JP S5735340A JP 11060680 A JP11060680 A JP 11060680A JP 11060680 A JP11060680 A JP 11060680A JP S5735340 A JPS5735340 A JP S5735340A
Authority
JP
Japan
Prior art keywords
oxide film
silicon
film
photoresist
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11060680A
Other languages
Japanese (ja)
Inventor
Fujiki Tokuyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11060680A priority Critical patent/JPS5735340A/en
Publication of JPS5735340A publication Critical patent/JPS5735340A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To compose an orthomorphic silicon etching region in an insulated seperation region without additional photo-etching process by the use of a laminated structure of a silicon nitride film and an insulation film. CONSTITUTION:A thermal oxide film 2, a silicon nitride film 3 and a silicone oxide film 4 are formed on a silicon semiconductor substrate 1 and photoresist 5 is coated. After the formation of a photoresist pattern 5, the silicon oxide film 4 is etched. After an etching of a silicon nitride film 3, the substrate 1 is heat-treated to soften the photoresist 5 so that it adheres closely to the silicon oxide film 2. Then an etched groove 6 is formed in the surface of the silicon substrate by etching the silicon oxide film 2 and the silicone substrate. After removing the photoresist and the silicon oxide film 4, an embeded silicone oxide film 7 is formed by masking with the silicon nitride film so that a silicon oxide film for insulating seperation is obtained.
JP11060680A 1980-08-12 1980-08-12 Manufacture of semiconductor device Pending JPS5735340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11060680A JPS5735340A (en) 1980-08-12 1980-08-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11060680A JPS5735340A (en) 1980-08-12 1980-08-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5735340A true JPS5735340A (en) 1982-02-25

Family

ID=14540093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11060680A Pending JPS5735340A (en) 1980-08-12 1980-08-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5735340A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0290546A (en) * 1988-09-27 1990-03-30 Matsushita Electric Works Ltd Manufacture of dielectric isolation substrate
JPH0684886U (en) * 1993-05-21 1994-12-06 株式会社ヤナギヤ Mixing material stirring device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0290546A (en) * 1988-09-27 1990-03-30 Matsushita Electric Works Ltd Manufacture of dielectric isolation substrate
JPH0684886U (en) * 1993-05-21 1994-12-06 株式会社ヤナギヤ Mixing material stirring device

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