[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS5633726A - Inter-computer channel connecting system - Google Patents

Inter-computer channel connecting system

Info

Publication number
JPS5633726A
JPS5633726A JP10811279A JP10811279A JPS5633726A JP S5633726 A JPS5633726 A JP S5633726A JP 10811279 A JP10811279 A JP 10811279A JP 10811279 A JP10811279 A JP 10811279A JP S5633726 A JPS5633726 A JP S5633726A
Authority
JP
Japan
Prior art keywords
reception
data
processor
register
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10811279A
Other languages
Japanese (ja)
Inventor
Mamoru Araya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10811279A priority Critical patent/JPS5633726A/en
Publication of JPS5633726A publication Critical patent/JPS5633726A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To avoid the useless channel transfer by prefetching the number of the transfer words sent from the processor of the remote side by the device of the receiving system and then realizing the security of the necessary data reception storing area as well as the disignation of the number of the received words.
CONSTITUTION: When the transmission start request signal WRIT START is turned on by the processor of transmission system, the initialization is given to the counter 12 through the gate 22 when the FF14 is off, i.g. the buffer register 10 is idle. And the data are stored successively into the register 10 by the data transfer signal WRIT STB, and then the end interruption is given by the transmission end signal SEND TERM. On the other hand, if the reception start request signal READ START is supplied to the gate during the reception, the data word number stored in the register 10 is prefetched through the gates 18 and 16 when the FF14 is on. And the processor of reception system takes in the reception signal READ STB by the number equivalent of the word number. Thus the useless channel transfer can be avoided by the word number prefetching control of the effective data to be received.
COPYRIGHT: (C)1981,JPO&Japio
JP10811279A 1979-08-27 1979-08-27 Inter-computer channel connecting system Pending JPS5633726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10811279A JPS5633726A (en) 1979-08-27 1979-08-27 Inter-computer channel connecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10811279A JPS5633726A (en) 1979-08-27 1979-08-27 Inter-computer channel connecting system

Publications (1)

Publication Number Publication Date
JPS5633726A true JPS5633726A (en) 1981-04-04

Family

ID=14476193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10811279A Pending JPS5633726A (en) 1979-08-27 1979-08-27 Inter-computer channel connecting system

Country Status (1)

Country Link
JP (1) JPS5633726A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212566A (en) * 1981-06-18 1982-12-27 Bendix Corp Link for exchanging data between master computer and slave computer and controlling of slave computer between main computer and slave computer
JPH0749842A (en) * 1993-12-27 1995-02-21 Hitachi Ltd Parallel processing computer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212566A (en) * 1981-06-18 1982-12-27 Bendix Corp Link for exchanging data between master computer and slave computer and controlling of slave computer between main computer and slave computer
JPH035626B2 (en) * 1981-06-18 1991-01-28 Bendix Corp
JPH0749842A (en) * 1993-12-27 1995-02-21 Hitachi Ltd Parallel processing computer

Similar Documents

Publication Publication Date Title
JPS6419438A (en) Hot stand-by memory copy system
WO1988006760A3 (en) Central processor unit for digital data processing system including write buffer management mechanism
JPS5790740A (en) Information transfer device
JPS5633726A (en) Inter-computer channel connecting system
JPS6470858A (en) Data transfer system
JPS54146555A (en) Data transfer system between processors
JPS53126828A (en) Storage control unit
JPS57197629A (en) Data transferring system
JPS57209525A (en) Access controlling system for channel buffer
JPS55105727A (en) Channel coupling system
JPS54151331A (en) Data processor
JPS5473534A (en) Inter-system connecting system
JPS5489434A (en) Memory access control processing system
JPS5474640A (en) Channel unit
JPS6448159A (en) Data prefetch system
JPS5741728A (en) Controlling system of data transfer
JPS57205881A (en) Trap controlling system
JPS6473458A (en) System for controlling access of vector data
JPS5380144A (en) Data transmission control system
JPS54103644A (en) Channel device
JPS5624626A (en) Data processing system
JPS5533273A (en) Channel control system
JPS56107378A (en) Cash controller
JPS5659337A (en) Data processing system
JPS5487140A (en) Data transfer control system