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JPS5621344A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5621344A
JPS5621344A JP9593579A JP9593579A JPS5621344A JP S5621344 A JPS5621344 A JP S5621344A JP 9593579 A JP9593579 A JP 9593579A JP 9593579 A JP9593579 A JP 9593579A JP S5621344 A JPS5621344 A JP S5621344A
Authority
JP
Japan
Prior art keywords
layer
wiring
impurity
taper
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9593579A
Other languages
Japanese (ja)
Inventor
Kouji Ariizumi
Masayuki Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9593579A priority Critical patent/JPS5621344A/en
Publication of JPS5621344A publication Critical patent/JPS5621344A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To manufacture an Al wiring of desired taper angle, by composing an Al layer of two or more layers and taking the impurity concentration of the Al layer into consideration. CONSTITUTION:The Al layer is composed of a pure Al layer 11 near a semiconductor substrate and an Al layer 12 farther from the substrate and containing an impurity such as Si. It is desirable that the ratio of the thickness of the layer 11 to that of the other layer 12 is set at 1 or more, because the etching rate of the impurity-containing Al layer is larger than that of the pure Al layer and the side face of the layer 12 is likely to become steep. For this reason, the thickness of the layer 12 having the steep side face is made as small as possible to perform etching. As a result, the Al wiring layer 1 of gentle taper is provided, the taper of a low-temperature oxidation film 3 laminated on the wiring layer 1 becomes gentle and the step breaking of another Al layer produced on the film 3 is provented.
JP9593579A 1979-07-27 1979-07-27 Semiconductor device and manufacture thereof Pending JPS5621344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9593579A JPS5621344A (en) 1979-07-27 1979-07-27 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9593579A JPS5621344A (en) 1979-07-27 1979-07-27 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5621344A true JPS5621344A (en) 1981-02-27

Family

ID=14151121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9593579A Pending JPS5621344A (en) 1979-07-27 1979-07-27 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5621344A (en)

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