JPS5617442A - Parity error processing system - Google Patents
Parity error processing systemInfo
- Publication number
- JPS5617442A JPS5617442A JP9213479A JP9213479A JPS5617442A JP S5617442 A JPS5617442 A JP S5617442A JP 9213479 A JP9213479 A JP 9213479A JP 9213479 A JP9213479 A JP 9213479A JP S5617442 A JPS5617442 A JP S5617442A
- Authority
- JP
- Japan
- Prior art keywords
- parity
- error
- processor
- processing
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Detection And Correction Of Errors (AREA)
Abstract
PURPOSE: To attain economical program constitution by making the processing of a processor different in accordance with the importance of data in which a parity error occurs.
CONSTITUTION: Parity-error adding and checking circuit 3 adds a parity bit when storing main memory 2 with information and makes a parity check when leading the information out of main memory 2. If a parity error is detected, an error detection signal is sent to parity-error processing circuit 7 through information line (q). Parity-error processing circuit 7 discriminates whether the parity error has been made in memory access from processor 1 or in the operation of DMA transfer circuit 6 and then reports the result to state display register 4. Processor 1 performs needed processing by looking in the contents of state display register 4.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54092134A JPS6042496B2 (en) | 1979-07-21 | 1979-07-21 | Parity error processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54092134A JPS6042496B2 (en) | 1979-07-21 | 1979-07-21 | Parity error processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5617442A true JPS5617442A (en) | 1981-02-19 |
JPS6042496B2 JPS6042496B2 (en) | 1985-09-24 |
Family
ID=14045954
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54092134A Expired JPS6042496B2 (en) | 1979-07-21 | 1979-07-21 | Parity error processing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6042496B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63282872A (en) * | 1987-05-15 | 1988-11-18 | Fujitsu Ltd | Data processor |
JPH06337820A (en) * | 1993-05-28 | 1994-12-06 | Internatl Business Mach Corp <Ibm> | Mechanism and method for detection and recovery of error in multiple bus system |
-
1979
- 1979-07-21 JP JP54092134A patent/JPS6042496B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63282872A (en) * | 1987-05-15 | 1988-11-18 | Fujitsu Ltd | Data processor |
JPH06337820A (en) * | 1993-05-28 | 1994-12-06 | Internatl Business Mach Corp <Ibm> | Mechanism and method for detection and recovery of error in multiple bus system |
Also Published As
Publication number | Publication date |
---|---|
JPS6042496B2 (en) | 1985-09-24 |
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