JPS56161662A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS56161662A JPS56161662A JP6390480A JP6390480A JPS56161662A JP S56161662 A JPS56161662 A JP S56161662A JP 6390480 A JP6390480 A JP 6390480A JP 6390480 A JP6390480 A JP 6390480A JP S56161662 A JPS56161662 A JP S56161662A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- bonded
- copper
- thermal
- carbon fiber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
PURPOSE:To prevent the thermal fatigue of a semiconductor device by securing a member having approximately equal thermal expansion coefficient to and larger thermal conductivity than an insulating substrate onto the substrate carrying elements, thereby reducing the thermal resistance of a high heating quantity device substrate. CONSTITUTION:A copper-carbon fiber composite substrate 4 (0.5mm. thick) is bonded with low melting point solder 5 onto the back surface of a device substrate 1 on which multiple chips are mounted by CCB bond or the like. A cap 11 is simultaneously sealed at this time, and the chip 2 is soldered in advance at a high temperature. With the substrate 14 as a heat sink fins 12 made, for example, of copper are divided and bonded, or the substrate is used also as fins in a shape 15 and is thus bonded to the substrate 1. Thus, a large-sized substrate which carries a high heating quantity part can incorporate low thermal resistance and high thermal fatigue resistance. The method employing the copper-carbon fiber material can also be similarly applied to the substrate of face-up type bonding.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6390480A JPS56161662A (en) | 1980-05-16 | 1980-05-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6390480A JPS56161662A (en) | 1980-05-16 | 1980-05-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56161662A true JPS56161662A (en) | 1981-12-12 |
Family
ID=13242768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6390480A Pending JPS56161662A (en) | 1980-05-16 | 1980-05-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56161662A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58164287A (en) * | 1982-03-24 | 1983-09-29 | 株式会社日立製作所 | Substrate for integrated circuit |
JPS594148A (en) * | 1982-06-30 | 1984-01-10 | Nec Corp | High density ceramic package |
-
1980
- 1980-05-16 JP JP6390480A patent/JPS56161662A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58164287A (en) * | 1982-03-24 | 1983-09-29 | 株式会社日立製作所 | Substrate for integrated circuit |
JPS594148A (en) * | 1982-06-30 | 1984-01-10 | Nec Corp | High density ceramic package |
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