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JPS56161662A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56161662A
JPS56161662A JP6390480A JP6390480A JPS56161662A JP S56161662 A JPS56161662 A JP S56161662A JP 6390480 A JP6390480 A JP 6390480A JP 6390480 A JP6390480 A JP 6390480A JP S56161662 A JPS56161662 A JP S56161662A
Authority
JP
Japan
Prior art keywords
substrate
bonded
copper
thermal
carbon fiber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6390480A
Other languages
Japanese (ja)
Inventor
Tasao Soga
Takuzo Ogawa
Tateo Tamamura
Akio Chiba
Seiki Shimizu
Masao Funiyu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6390480A priority Critical patent/JPS56161662A/en
Publication of JPS56161662A publication Critical patent/JPS56161662A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the thermal fatigue of a semiconductor device by securing a member having approximately equal thermal expansion coefficient to and larger thermal conductivity than an insulating substrate onto the substrate carrying elements, thereby reducing the thermal resistance of a high heating quantity device substrate. CONSTITUTION:A copper-carbon fiber composite substrate 4 (0.5mm. thick) is bonded with low melting point solder 5 onto the back surface of a device substrate 1 on which multiple chips are mounted by CCB bond or the like. A cap 11 is simultaneously sealed at this time, and the chip 2 is soldered in advance at a high temperature. With the substrate 14 as a heat sink fins 12 made, for example, of copper are divided and bonded, or the substrate is used also as fins in a shape 15 and is thus bonded to the substrate 1. Thus, a large-sized substrate which carries a high heating quantity part can incorporate low thermal resistance and high thermal fatigue resistance. The method employing the copper-carbon fiber material can also be similarly applied to the substrate of face-up type bonding.
JP6390480A 1980-05-16 1980-05-16 Semiconductor device Pending JPS56161662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6390480A JPS56161662A (en) 1980-05-16 1980-05-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6390480A JPS56161662A (en) 1980-05-16 1980-05-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56161662A true JPS56161662A (en) 1981-12-12

Family

ID=13242768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6390480A Pending JPS56161662A (en) 1980-05-16 1980-05-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56161662A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58164287A (en) * 1982-03-24 1983-09-29 株式会社日立製作所 Substrate for integrated circuit
JPS594148A (en) * 1982-06-30 1984-01-10 Nec Corp High density ceramic package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58164287A (en) * 1982-03-24 1983-09-29 株式会社日立製作所 Substrate for integrated circuit
JPS594148A (en) * 1982-06-30 1984-01-10 Nec Corp High density ceramic package

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