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JPS56104545A - Division ratio setting circuit of pll - Google Patents

Division ratio setting circuit of pll

Info

Publication number
JPS56104545A
JPS56104545A JP793980A JP793980A JPS56104545A JP S56104545 A JPS56104545 A JP S56104545A JP 793980 A JP793980 A JP 793980A JP 793980 A JP793980 A JP 793980A JP S56104545 A JPS56104545 A JP S56104545A
Authority
JP
Japan
Prior art keywords
division ratio
programmable divider
memory
pll
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP793980A
Other languages
Japanese (ja)
Inventor
Hiroshi Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP793980A priority Critical patent/JPS56104545A/en
Publication of JPS56104545A publication Critical patent/JPS56104545A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To vary the division ratio of a programmable divider, by connecting previously an up-down counter to the programmable divider and varying the contents of the up-down counter. CONSTITUTION:In case the signal of fi=kHz is applied to the input of the phase detector 1, the frequency fO of the VCO3 is changed into 5MHz. For this purpose, the division ratio is set as N=5,000 for the programmable divider 6. The thumb- wheel switch of the division ratio setter 5 is set at 5,000, and the switch 11 is connected to the LOW side. In such way, 5,000 is stored in the memory 6 and then applied to the programmable divider 4 to obtain a division ratio of 5,000. To obtain a frequency higher than the set 5MHz by 10kHz, the switch 9 is connected 10 times to the LOW side. As a result, a signal of 10 pulses is generated from the monostable multivibrator 7 and applied to the UP input terminal of the memory 6. Thus the memory 6 receives a 10-addition.
JP793980A 1980-01-25 1980-01-25 Division ratio setting circuit of pll Pending JPS56104545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP793980A JPS56104545A (en) 1980-01-25 1980-01-25 Division ratio setting circuit of pll

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP793980A JPS56104545A (en) 1980-01-25 1980-01-25 Division ratio setting circuit of pll

Publications (1)

Publication Number Publication Date
JPS56104545A true JPS56104545A (en) 1981-08-20

Family

ID=11679473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP793980A Pending JPS56104545A (en) 1980-01-25 1980-01-25 Division ratio setting circuit of pll

Country Status (1)

Country Link
JP (1) JPS56104545A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59171436U (en) * 1983-04-30 1984-11-16 カシオ計算機株式会社 variable frequency generator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS545319A (en) * 1977-06-15 1979-01-16 Hitachi Ltd Transceiver of multi-channel

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS545319A (en) * 1977-06-15 1979-01-16 Hitachi Ltd Transceiver of multi-channel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59171436U (en) * 1983-04-30 1984-11-16 カシオ計算機株式会社 variable frequency generator

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