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JPS5578348A - False fault generation system - Google Patents

False fault generation system

Info

Publication number
JPS5578348A
JPS5578348A JP15102678A JP15102678A JPS5578348A JP S5578348 A JPS5578348 A JP S5578348A JP 15102678 A JP15102678 A JP 15102678A JP 15102678 A JP15102678 A JP 15102678A JP S5578348 A JPS5578348 A JP S5578348A
Authority
JP
Japan
Prior art keywords
value
register
data transfer
false fault
false
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15102678A
Other languages
Japanese (ja)
Other versions
JPS6051744B2 (en
Inventor
Takeshi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53151026A priority Critical patent/JPS6051744B2/en
Publication of JPS5578348A publication Critical patent/JPS5578348A/en
Publication of JPS6051744B2 publication Critical patent/JPS6051744B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To facilitate error cause examination by comparing the value of a register and the value of a byte counter with each other and stopping data transfer to generate false signals when a coincidence signal is outputted.
CONSTITUTION: An arbitrary value can be set to register 2, and the value of register 2 is compared with the value of byte counter 1 by comparator circuit 3. When a channel unit performs data transfer for an I/O device, etc., data transfer is stopped to generate a false fault state when a coincidence signal is outputted from circuit 3. As a result, error cause examination can be facilitated by generating the false fault state at an arbitrary timing.
COPYRIGHT: (C)1980,JPO&Japio
JP53151026A 1978-12-08 1978-12-08 Simulated failure generation method Expired JPS6051744B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53151026A JPS6051744B2 (en) 1978-12-08 1978-12-08 Simulated failure generation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53151026A JPS6051744B2 (en) 1978-12-08 1978-12-08 Simulated failure generation method

Publications (2)

Publication Number Publication Date
JPS5578348A true JPS5578348A (en) 1980-06-12
JPS6051744B2 JPS6051744B2 (en) 1985-11-15

Family

ID=15509670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53151026A Expired JPS6051744B2 (en) 1978-12-08 1978-12-08 Simulated failure generation method

Country Status (1)

Country Link
JP (1) JPS6051744B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62134739A (en) * 1985-12-06 1987-06-17 Fujitsu Ltd Artificial error generating circuit
JPH0273433A (en) * 1988-09-09 1990-03-13 Nec Corp Data transfer device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62244235A (en) * 1986-04-17 1987-10-24 株式会社日立製作所 Electric source

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62134739A (en) * 1985-12-06 1987-06-17 Fujitsu Ltd Artificial error generating circuit
JPH0273433A (en) * 1988-09-09 1990-03-13 Nec Corp Data transfer device

Also Published As

Publication number Publication date
JPS6051744B2 (en) 1985-11-15

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